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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <types.h>
Go to the source code of this file.
Data Structures | |
struct | rk3399_ddr_pctl_regs |
struct | rk3399_ddr_publ_regs |
struct | rk3399_ddr_pi_regs |
union | noc_ddrtiminga0 |
union | noc_ddrtimingb0 |
union | noc_ddrtimingc0 |
union | noc_devtodev0 |
union | noc_ddrmode |
struct | rk3399_msch_regs |
struct | rk3399_msch_timings |
struct | rk3399_ddr_cic_regs |
struct | rk3399_sdram_channel |
struct | rk3399_sdram_params |
Macros | |
#define | START (1) |
#define | PWRUP_SREFRESH_EXIT (1 << 16) |
#define | MEM_RST_VALID (1) |
#define | PI_CA_TRAINING (1 << 0) |
#define | PI_WRITE_LEVELING (1 << 1) |
#define | PI_READ_GATE_TRAINING (1 << 2) |
#define | PI_READ_LEVELING (1 << 3) |
#define | PI_WDQ_LEVELING (1 << 4) |
#define | PI_FULL_TRAINING (0xff) |
Enumerations | |
enum | { DDR3 = 3 , LPDDR2 = 5 , LPDDR3 = 6 , LPDDR4 = 7 , UNUSED = 0xFF } |
Functions | |
void | sdram_init (const struct rk3399_sdram_params *sdram_params) |
u32 | sdram_get_ram_code (void) |
const struct rk3399_sdram_params * | get_sdram_config (void) |
size_t | sdram_size_mb (void) |
const struct rk3399_sdram_params* get_sdram_config | ( | void | ) |
Definition at line 85 of file sdram_configs.c.
References ARRAY_SIZE, BIOS_SPEW, cbfs_load(), die(), rk3288_sdram_params::dramtype, get_sdram_target_mhz(), sdram_params::MemoryType, name, NULL, NvBootMemoryType_Unused, params, printk, ram_code(), sdram_configs, sdram_get_ram_code(), snprintf(), type, TYPE_INVALID, and UNUSED.
Referenced by main(), mt_mem_init(), mt_mem_init_run(), platform_romstage_main(), and romstage().
Definition at line 601 of file sdram.c.
References misc, apbmisc::pp_strapping_opt_a, PP_STRAPPING_OPT_A_RAM_CODE_MASK, PP_STRAPPING_OPT_A_RAM_CODE_SHIFT, read32(), and TEGRA_APB_MISC_BASE.
void sdram_init | ( | const struct rk3399_sdram_params * | sdram_params | ) |
Definition at line 1109 of file sdram.c.
References BIOS_ERR, BIOS_INFO, board_reset(), data_training(), DDR3, die(), dram_all_config(), LPDDR3, LPDDR4, MHz, params, pctl_cfg(), phy_dll_bypass_set(), phy_pctrl_reset(), PI_FULL_TRAINING, printk, rk3399_ddr_publ, rkclk_configure_ddr(), set_ddrconfig(), switch_to_phy_index1(), and udelay().