coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/romstage.h>
4 #include <spd_bin.h>
5 #include <string.h>
6 
7 static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
8 {
9  const u16 RcompResistor[3] = {121, 81, 100};
10  memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
11 }
12 
13 static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
14 {
15  const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
16  memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
17 }
18 
19 void mainboard_memory_init_params(FSPM_UPD *mupd)
20 {
21  FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
22 
23  struct spd_block blk = {
24  .addr_map = {0x50, 0x52},
25  };
26 
27  get_spd_smbus(&blk);
28  dump_spd_info(&blk);
29 
30  mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
31  mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
32 
33  mem_cfg->DqPinsInterleaved = TRUE;
34  mem_cfg->CaVrefConfig = 2;
35  mem_cfg->MemorySpdDataLen = blk.len;
36  mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
37  mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
38 }
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
Definition: romstage.c:7
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
Definition: romstage.c:13
void get_spd_smbus(struct spd_block *blk)
Definition: smbuslib.c:72
void dump_spd_info(struct spd_block *blk)
Definition: spd_bin.c:10
unsigned long uintptr_t
Definition: stdint.h:21
uint16_t u16
Definition: stdint.h:48
Definition: ddr4.c:86
u8 addr_map[CONFIG_DIMM_MAX]
Definition: spd_bin.h:39
u8 * spd_array[CONFIG_DIMM_MAX]
Definition: spd_bin.h:40
uint16_t len
Definition: ddr4.c:89