#include <chip.h>

Collaboration diagram for southbridge_intel_bd82x6x_config:

Data Fields
uint8_t	gpi0_routing
	GPI Routing configuration. More...

uint8_t	gpi1_routing

uint8_t	gpi2_routing

uint8_t	gpi3_routing

uint8_t	gpi4_routing

uint8_t	gpi5_routing

uint8_t	gpi6_routing

uint8_t	gpi7_routing

uint8_t	gpi8_routing

uint8_t	gpi9_routing

uint8_t	gpi10_routing

uint8_t	gpi11_routing

uint8_t	gpi12_routing

uint8_t	gpi13_routing

uint8_t	gpi14_routing

uint8_t	gpi15_routing

uint32_t	gpe0_en

uint16_t	alt_gp_smi_en

uint8_t	sata_port_map

uint32_t	sata_port0_gen3_tx

uint32_t	sata_port1_gen3_tx

uint8_t	sata_interface_speed_support
	SATA Interface Speed Support Configuration. More...

uint32_t	gen1_dec

uint32_t	gen2_dec

uint32_t	gen3_dec

uint32_t	gen4_dec

bool	pcie_port_coalesce

uint8_t	pcie_aspm [8]

int	docking_supported

uint8_t	pcie_hotplug_map [8]

uint32_t	xhci_switchable_ports

uint32_t	superspeed_capable_ports

uint32_t	xhci_overcurrent_mapping

uint32_t	spi_uvscc

uint32_t	spi_lvscc

struct intel_swseq_spi_config	spi

Detailed Description

Definition at line 9 of file chip.h.

Field Documentation

◆ alt_gp_smi_en

uint16_t southbridge_intel_bd82x6x_config::alt_gp_smi_en

Definition at line 37 of file chip.h.

◆ docking_supported

int southbridge_intel_bd82x6x_config::docking_supported

Definition at line 66 of file chip.h.

◆ gen1_dec

uint32_t southbridge_intel_bd82x6x_config::gen1_dec

Definition at line 55 of file chip.h.

◆ gen2_dec

uint32_t southbridge_intel_bd82x6x_config::gen2_dec

Definition at line 56 of file chip.h.

◆ gen3_dec

uint32_t southbridge_intel_bd82x6x_config::gen3_dec

Definition at line 57 of file chip.h.

◆ gen4_dec

uint32_t southbridge_intel_bd82x6x_config::gen4_dec

Definition at line 58 of file chip.h.

◆ gpe0_en

uint32_t southbridge_intel_bd82x6x_config::gpe0_en

Definition at line 36 of file chip.h.

◆ gpi0_routing

uint8_t southbridge_intel_bd82x6x_config::gpi0_routing

GPI Routing configuration.

Only the lower two bits have a meaning: 00: No effect 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10: SCI (if corresponding GPIO_EN bit is also set) 11: reserved

Definition at line 19 of file chip.h.

◆ gpi10_routing

uint8_t southbridge_intel_bd82x6x_config::gpi10_routing

Definition at line 29 of file chip.h.

◆ gpi11_routing

uint8_t southbridge_intel_bd82x6x_config::gpi11_routing

Definition at line 30 of file chip.h.

◆ gpi12_routing

uint8_t southbridge_intel_bd82x6x_config::gpi12_routing

Definition at line 31 of file chip.h.

◆ gpi13_routing

uint8_t southbridge_intel_bd82x6x_config::gpi13_routing

Definition at line 32 of file chip.h.

◆ gpi14_routing

uint8_t southbridge_intel_bd82x6x_config::gpi14_routing

Definition at line 33 of file chip.h.

◆ gpi15_routing

uint8_t southbridge_intel_bd82x6x_config::gpi15_routing

Definition at line 34 of file chip.h.

◆ gpi1_routing

uint8_t southbridge_intel_bd82x6x_config::gpi1_routing

Definition at line 20 of file chip.h.

◆ gpi2_routing

uint8_t southbridge_intel_bd82x6x_config::gpi2_routing

Definition at line 21 of file chip.h.

◆ gpi3_routing

uint8_t southbridge_intel_bd82x6x_config::gpi3_routing

Definition at line 22 of file chip.h.

◆ gpi4_routing

uint8_t southbridge_intel_bd82x6x_config::gpi4_routing

Definition at line 23 of file chip.h.

◆ gpi5_routing

uint8_t southbridge_intel_bd82x6x_config::gpi5_routing

Definition at line 24 of file chip.h.

◆ gpi6_routing

uint8_t southbridge_intel_bd82x6x_config::gpi6_routing

Definition at line 25 of file chip.h.

◆ gpi7_routing

uint8_t southbridge_intel_bd82x6x_config::gpi7_routing

Definition at line 26 of file chip.h.

◆ gpi8_routing

uint8_t southbridge_intel_bd82x6x_config::gpi8_routing

Definition at line 27 of file chip.h.

◆ gpi9_routing

uint8_t southbridge_intel_bd82x6x_config::gpi9_routing

Definition at line 28 of file chip.h.

◆ pcie_aspm

uint8_t southbridge_intel_bd82x6x_config::pcie_aspm[8]

Definition at line 64 of file chip.h.

◆ pcie_hotplug_map

uint8_t southbridge_intel_bd82x6x_config::pcie_hotplug_map[8]

Definition at line 68 of file chip.h.

◆ pcie_port_coalesce

bool southbridge_intel_bd82x6x_config::pcie_port_coalesce

Definition at line 61 of file chip.h.

◆ sata_interface_speed_support

uint8_t southbridge_intel_bd82x6x_config::sata_interface_speed_support

SATA Interface Speed Support Configuration.

Only the lower two bits have a meaning: 00 - No effect (leave as chip default) 01 - 1.5 Gb/s maximum speed 10 - 3.0 Gb/s maximum speed 11 - 6.0 Gb/s maximum speed

Definition at line 53 of file chip.h.

◆ sata_port0_gen3_tx

uint32_t southbridge_intel_bd82x6x_config::sata_port0_gen3_tx

Definition at line 41 of file chip.h.

◆ sata_port1_gen3_tx

uint32_t southbridge_intel_bd82x6x_config::sata_port1_gen3_tx

Definition at line 42 of file chip.h.

◆ sata_port_map

uint8_t southbridge_intel_bd82x6x_config::sata_port_map

Definition at line 40 of file chip.h.

◆ spi

struct intel_swseq_spi_config southbridge_intel_bd82x6x_config::spi

Definition at line 78 of file chip.h.

◆ spi_lvscc

uint32_t southbridge_intel_bd82x6x_config::spi_lvscc