3 #ifndef __SOC_NVIDIA_TEGRA210_MC_H__
4 #define __SOC_NVIDIA_TEGRA210_MC_H__
210 #define MC_SECURITY_CARVEOUT_LOCKED (1 << 1)
211 #define MC_VPR_WR_ACCESS_DISABLE (1 << 0)
212 #define MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE (1 << 1)
uint32_t emem_adr_cfg_channel_mask
uint32_t security_carveout1_cfia1
uint32_t security_carveout5_cfia3
uint32_t security_carveout2_ca3
uint32_t security_carveout3_ca1
uint32_t security_carveout1_ca1
uint32_t security_carveout4_cfia2
uint32_t display_snap_ring
uint32_t security_carveout2_size_128kb
uint32_t security_carveout5_ca0
uint32_t emem_arb_isochronous_0
uint32_t security_carveout1_cfg0
uint32_t emem_arb_timing_rcd
uint32_t security_carveout2_ca1
uint32_t security_carveout1_ca2
uint32_t emem_cfg_access_ctrl
uint32_t video_protect_size_mb
uint32_t security_carveout1_ca4
uint32_t emem_arb_timing_rfcpb
uint32_t security_carveout5_ca3
uint32_t security_carveout2_cfia0
uint32_t timing_control_dbg
uint32_t security_carveout2_bom
uint32_t emem_arb_isochronous_2
uint32_t security_carveout5_cfia4
uint32_t emem_arb_timing_rap2pre
uint32_t sec_carveout_size_mb
uint32_t emem_arb_timing_r2r
uint32_t emem_arb_override
uint32_t emem_arb_ring3_throttle
uint32_t security_carveout3_cfia4
uint32_t security_carveout5_size_128kb
uint32_t security_carveout2_cfia1
uint32_t video_protect_vpr_override
uint32_t emem_arb_outstanding_req
uint32_t mts_carveout_adr_hi
uint32_t video_protect_bom_adr_hi
uint32_t security_carveout3_ca4
uint32_t security_carveout3_bom
uint32_t security_carveout3_size_128kb
uint32_t sec_carveout_reg_ctrl
uint32_t security_carveout4_cfia4
uint32_t emem_adr_cfg_dev1
uint32_t security_carveout1_bom_hi
uint32_t security_carveout4_ca3
uint32_t security_carveout1_cfia3
uint32_t security_carveout3_cfia0
uint32_t security_carveout5_ca4
uint32_t security_carveout3_cfg0
uint32_t emem_adr_cfg_dev0
uint32_t emem_adr_cfg_bank_mask_1
uint32_t security_carveout2_cfia3
uint32_t security_carveout2_ca2
uint32_t emem_bank_swizzle_cfg0
uint32_t security_carveout3_cfia1
uint32_t security_carveout1_cfia0
uint32_t security_carveout2_bom_hi
uint32_t emem_arb_timing_ras
uint32_t security_carveout3_ca3
uint32_t security_carveout3_ca0
uint32_t video_protect_gpu_override_0
uint32_t security_carveout1_bom
uint32_t security_carveout4_cfg0
uint32_t video_protect_bom
uint32_t emem_arb_timing_rc
uint32_t emem_arb_isochronous_1
uint32_t emem_adr_cfg_bank_mask_0
uint32_t emem_adr_cfg_bank_mask_2
uint32_t security_carveout4_bom
uint32_t emem_arb_timing_w2w
uint32_t emem_arb_ring1_throttle
uint32_t security_carveout4_ca1
uint32_t security_carveout4_cfia0
uint32_t security_carveout3_cfia3
uint32_t security_carveout1_cfia2
uint32_t security_carveout5_cfia1
uint32_t security_carveout4_ca2
uint32_t emem_bank_swizzle_cfg1
uint32_t emem_arb_da_turns
uint32_t emem_arb_refpb_hp_ctrl
uint32_t security_carveout4_size_128kb
uint32_t security_carveout5_cfia2
uint32_t security_carveout5_ca2
uint32_t emem_bank_swizzle_cfg3
uint32_t video_protect_gpu_override_1
uint32_t security_carveout2_ca4
uint32_t security_carveout2_ca0
uint32_t security_carveout1_ca3
uint32_t mts_carveout_reg_ctrl
uint32_t security_carveout5_cfg0
uint32_t emem_arb_override_1
uint32_t emem_arb_da_covers
uint32_t security_carveout3_ca2
uint32_t security_carveout5_cfia0
uint32_t security_carveout3_bom_hi
uint32_t video_protect_vpr_override1
uint32_t security_carveout5_bom
uint32_t emem_arb_timing_ccdmw
uint32_t mts_carveout_bom
uint32_t emem_bank_swizzle_cfg2
uint32_t sec_carveout_bom
uint32_t security_carveout2_cfia2
uint32_t sec_carveout_adr_hi
uint32_t security_carveout1_size_128kb
uint32_t security_carveout4_ca4
uint32_t security_carveout5_bom_hi
uint32_t emem_arb_timing_faw
uint32_t emem_arb_timing_wap2pre
uint32_t security_carveout4_bom_hi
uint32_t security_carveout4_cfia3
uint32_t emem_arb_timing_w2r
uint32_t security_carveout3_cfia2
uint32_t dis_extra_snap_levels
uint32_t security_carveout4_cfia1
uint32_t security_carveout5_ca1
uint32_t emem_arb_timing_rp
uint32_t video_protect_reg_ctrl
uint32_t mts_carveout_size_mb
uint32_t security_carveout2_cfg0
uint32_t emem_arb_refpb_bank_ctrl
uint32_t emem_arb_timing_r2w
uint32_t emem_arb_timing_rrd
uint32_t security_carveout2_cfia4
uint32_t security_carveout4_ca0
uint32_t security_carveout1_cfia4
uint32_t security_carveout1_ca0
check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4)
@ MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT
@ MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED
@ MC_EMEM_CFG_SIZE_MB_SHIFT
@ MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK
@ MC_TIMING_CONTROL_TIMING_UPDATE
@ MC_EMEM_CFG_SIZE_MB_MASK