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◆ AP_CVMMEMCTL0_EL1_CCLKFORCE
#define AP_CVMMEMCTL0_EL1_CCLKFORCE (1 << 1) |
◆ AP_CVMMEMCTL0_EL1_DMBSTALLFORCE
#define AP_CVMMEMCTL0_EL1_DMBSTALLFORCE (1 << 55) |
◆ AP_CVMMEMCTL0_EL1_DVCA47
#define AP_CVMMEMCTL0_EL1_DVCA47 (1 << 37) |
◆ AP_CVMMEMCTL0_EL1_GSYNCTO_MASK
#define AP_CVMMEMCTL0_EL1_GSYNCTO_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_GSYNCTO_SHIFT
#define AP_CVMMEMCTL0_EL1_GSYNCTO_SHIFT 48 |
◆ AP_CVMMEMCTL0_EL1_LDIL2CDIS
#define AP_CVMMEMCTL0_EL1_LDIL2CDIS (1 << 38) |
◆ AP_CVMMEMCTL0_EL1_LDPREFDIS
#define AP_CVMMEMCTL0_EL1_LDPREFDIS (1 << 35) |
◆ AP_CVMMEMCTL0_EL1_MCLKFORCE
#define AP_CVMMEMCTL0_EL1_MCLKFORCE (1 << 0) |
◆ AP_CVMMEMCTL0_EL1_NODE_MASK
#define AP_CVMMEMCTL0_EL1_NODE_MASK 0x3 |
◆ AP_CVMMEMCTL0_EL1_NODE_SHIFT
#define AP_CVMMEMCTL0_EL1_NODE_SHIFT 61 |
◆ AP_CVMMEMCTL0_EL1_RBFSHORTTO_MASK
#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_RBFSHORTTO_SHIFT
#define AP_CVMMEMCTL0_EL1_RBFSHORTTO_SHIFT 26 |
◆ AP_CVMMEMCTL0_EL1_RBFTO_MASK
#define AP_CVMMEMCTL0_EL1_RBFTO_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_RBFTO_SHIFT
#define AP_CVMMEMCTL0_EL1_RBFTO_SHIFT 21 |
◆ AP_CVMMEMCTL0_EL1_REPLAYPREFDIS
#define AP_CVMMEMCTL0_EL1_REPLAYPREFDIS (1 << 40) |
◆ AP_CVMMEMCTL0_EL1_STEXFAILCNT_MASK
#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_MASK 0x7 |
◆ AP_CVMMEMCTL0_EL1_STEXFAILCNT_SHIFT
#define AP_CVMMEMCTL0_EL1_STEXFAILCNT_SHIFT 58 |
◆ AP_CVMMEMCTL0_EL1_STEXL2CFORCE
#define AP_CVMMEMCTL0_EL1_STEXL2CFORCE (1 << 43) |
◆ AP_CVMMEMCTL0_EL1_STLSTALLFORCE
#define AP_CVMMEMCTL0_EL1_STLSTALLFORCE (1 << 56) |
◆ AP_CVMMEMCTL0_EL1_STPREFDIS
#define AP_CVMMEMCTL0_EL1_STPREFDIS (1 << 36) |
◆ AP_CVMMEMCTL0_EL1_TLBIALL
#define AP_CVMMEMCTL0_EL1_TLBIALL (1 << 46) |
◆ AP_CVMMEMCTL0_EL1_TLBIICFLUSH
#define AP_CVMMEMCTL0_EL1_TLBIICFLUSH (1 << 53) |
◆ AP_CVMMEMCTL0_EL1_TLBINOPDIS
#define AP_CVMMEMCTL0_EL1_TLBINOPDIS (1 << 54) |
◆ AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_MASK
#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_SHIFT
#define AP_CVMMEMCTL0_EL1_UTLBENTRIESM1_SHIFT 2 |
◆ AP_CVMMEMCTL0_EL1_UTLBFILLBYPDIS
#define AP_CVMMEMCTL0_EL1_UTLBFILLBYPDIS (1 << 47) |
◆ AP_CVMMEMCTL0_EL1_WBFALLBARRIER
#define AP_CVMMEMCTL0_EL1_WBFALLBARRIER (1 << 20) |
◆ AP_CVMMEMCTL0_EL1_WBFDMBFLUSHNEXT
#define AP_CVMMEMCTL0_EL1_WBFDMBFLUSHNEXT (1 << 44) |
◆ AP_CVMMEMCTL0_EL1_WBFDSBFLUSHALL
#define AP_CVMMEMCTL0_EL1_WBFDSBFLUSHALL (1 << 45) |
◆ AP_CVMMEMCTL0_EL1_WBFNOMERGE
#define AP_CVMMEMCTL0_EL1_WBFNOMERGE (1 << 19) |
◆ AP_CVMMEMCTL0_EL1_WBFTHRESH_MASK
#define AP_CVMMEMCTL0_EL1_WBFTHRESH_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_WBFTHRESH_SHIFT
#define AP_CVMMEMCTL0_EL1_WBFTHRESH_SHIFT 7 |
◆ AP_CVMMEMCTL0_EL1_WBFTO_MASK
#define AP_CVMMEMCTL0_EL1_WBFTO_MASK 0x1f |
◆ AP_CVMMEMCTL0_EL1_WBFTO_SHIFT
#define AP_CVMMEMCTL0_EL1_WBFTO_SHIFT 12 |
◆ AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA
#define AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA (1 << 17) |
◆ AP_CVMMEMCTL0_EL1_WBFTONSHENA
#define AP_CVMMEMCTL0_EL1_WBFTONSHENA (1 << 18) |
◆ AP_CVMMEMCTL0_EL1_WCUMISSFORCE
#define AP_CVMMEMCTL0_EL1_WCUMISSFORCE (1 << 41) |
◆ AP_CVMMEMCTL0_EL1_WFELDEX1DIS
#define AP_CVMMEMCTL0_EL1_WFELDEX1DIS (1 << 57) |
◆ AP_CVMMEMCTL0_EL1_WFILDEXDIS
#define AP_CVMMEMCTL0_EL1_WFILDEXDIS (1 << 34) |
◆ AP_CVMMEMCTL0_EL1_WFITO_MASK
#define AP_CVMMEMCTL0_EL1_WFITO_MASK 0x7 |
◆ AP_CVMMEMCTL0_EL1_WFITO_SHIFT
#define AP_CVMMEMCTL0_EL1_WFITO_SHIFT 31 |
◆ AP_CVMMEMCTL0_EL1_ZVAL2CDIS
#define AP_CVMMEMCTL0_EL1_ZVAL2CDIS (1 << 39) |