coreboot
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iocfg.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8195_IOCFG_H__
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#define __SOC_MEDIATEK_MT8195_IOCFG_H__
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#include <soc/addressmap.h>
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#include <types.h>
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struct
mt8195_iocfg_bm_regs
{
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u32
reserved1
[4];
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u32
drv_cfg1
;
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u32
drv_cfg1_set
;
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u32
drv_cfg1_clr
;
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u32
reserved2
;
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u32
drv_cfg2
;
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u32
drv_cfg2_set
;
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u32
drv_cfg2_clr
;
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u32
reserved3
;
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u32
drv_cfg3
;
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u32
drv_cfg3_set
;
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u32
drv_cfg3_clr
;
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u32
reserved4
[1];
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u32
eh_cfg
;
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u32
eh_cfg_set
;
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u32
eh_cfg_clr
;
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u32
reserved5
[9];
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u32
ies_cfg1
;
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u32
ies_cfg1_set
;
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u32
ies_cfg1_clr
;
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u32
reserved6
[5];
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u32
pd_cfg1
;
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u32
pd_cfg1_set
;
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u32
pd_cfg1_clr
;
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u32
reserved7
[5];
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u32
pu_cfg1
;
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u32
pu_cfg1_set
;
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u32
pu_cfg1_clr
;
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u32
reserved8
[1];
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u32
rdsel_cfg0
;
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u32
rdsel_cfg0_set
;
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u32
rdsel_cfg0_clr
;
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u32
reserved9
[9];
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u32
smt_cfg0
;
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u32
smt_cfg0_set
;
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u32
smt_cfg0_clr
;
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u32
reserved10
[5];
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u32
tdsel_cfg1
;
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u32
tdsel_cfg1_set
;
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u32
tdsel_cfg1_clr
;
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};
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check_member
(
mt8195_iocfg_bm_regs
, drv_cfg1, 0x10);
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check_member
(
mt8195_iocfg_bm_regs
, drv_cfg2, 0x20);
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check_member
(
mt8195_iocfg_bm_regs
, drv_cfg3, 0x30);
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check_member
(
mt8195_iocfg_bm_regs
, eh_cfg, 0x40);
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check_member
(
mt8195_iocfg_bm_regs
, ies_cfg1, 0x70);
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check_member
(
mt8195_iocfg_bm_regs
, pd_cfg1, 0x90);
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check_member
(
mt8195_iocfg_bm_regs
, pu_cfg1, 0xB0);
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check_member
(
mt8195_iocfg_bm_regs
, rdsel_cfg0, 0xC0);
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check_member
(
mt8195_iocfg_bm_regs
, smt_cfg0, 0xF0);
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check_member
(
mt8195_iocfg_bm_regs
, tdsel_cfg1, 0x110);
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#define mtk_iocfg_bm ((struct mt8195_iocfg_bm_regs *)IOCFG_BM_BASE)
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enum
{
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IO_4_MA
= 0x9,
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IO_6_MA
= 0x1b,
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};
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#endif
/* __SOC_MEDIATEK_MT8195_IOCFG_H__ */
IO_4_MA
@ IO_4_MA
Definition:
iocfg.h:16
check_member
check_member(mt8192_iocfg_lm_regs, drv_cfg1, 0x10)
IO_6_MA
@ IO_6_MA
Definition:
iocfg.h:66
u32
uint32_t u32
Definition:
stdint.h:51
mt8195_iocfg_bm_regs
Definition:
iocfg.h:9
mt8195_iocfg_bm_regs::rdsel_cfg0_set
u32 rdsel_cfg0_set
Definition:
iocfg.h:40
mt8195_iocfg_bm_regs::ies_cfg1_clr
u32 ies_cfg1_clr
Definition:
iocfg.h:29
mt8195_iocfg_bm_regs::tdsel_cfg1_set
u32 tdsel_cfg1_set
Definition:
iocfg.h:48
mt8195_iocfg_bm_regs::tdsel_cfg1_clr
u32 tdsel_cfg1_clr
Definition:
iocfg.h:49
mt8195_iocfg_bm_regs::reserved10
u32 reserved10[5]
Definition:
iocfg.h:46
mt8195_iocfg_bm_regs::drv_cfg3
u32 drv_cfg3
Definition:
iocfg.h:19
mt8195_iocfg_bm_regs::reserved3
u32 reserved3
Definition:
iocfg.h:18
mt8195_iocfg_bm_regs::ies_cfg1
u32 ies_cfg1
Definition:
iocfg.h:27
mt8195_iocfg_bm_regs::smt_cfg0_set
u32 smt_cfg0_set
Definition:
iocfg.h:44
mt8195_iocfg_bm_regs::reserved1
u32 reserved1[4]
Definition:
iocfg.h:10
mt8195_iocfg_bm_regs::reserved6
u32 reserved6[5]
Definition:
iocfg.h:30
mt8195_iocfg_bm_regs::reserved9
u32 reserved9[9]
Definition:
iocfg.h:42
mt8195_iocfg_bm_regs::tdsel_cfg1
u32 tdsel_cfg1
Definition:
iocfg.h:47
mt8195_iocfg_bm_regs::drv_cfg1
u32 drv_cfg1
Definition:
iocfg.h:11
mt8195_iocfg_bm_regs::reserved8
u32 reserved8[1]
Definition:
iocfg.h:38
mt8195_iocfg_bm_regs::pd_cfg1
u32 pd_cfg1
Definition:
iocfg.h:31
mt8195_iocfg_bm_regs::drv_cfg3_set
u32 drv_cfg3_set
Definition:
iocfg.h:20
mt8195_iocfg_bm_regs::smt_cfg0_clr
u32 smt_cfg0_clr
Definition:
iocfg.h:45
mt8195_iocfg_bm_regs::drv_cfg2_set
u32 drv_cfg2_set
Definition:
iocfg.h:16
mt8195_iocfg_bm_regs::reserved7
u32 reserved7[5]
Definition:
iocfg.h:34
mt8195_iocfg_bm_regs::eh_cfg
u32 eh_cfg
Definition:
iocfg.h:23
mt8195_iocfg_bm_regs::rdsel_cfg0_clr
u32 rdsel_cfg0_clr
Definition:
iocfg.h:41
mt8195_iocfg_bm_regs::rdsel_cfg0
u32 rdsel_cfg0
Definition:
iocfg.h:39
mt8195_iocfg_bm_regs::pu_cfg1_set
u32 pu_cfg1_set
Definition:
iocfg.h:36
mt8195_iocfg_bm_regs::ies_cfg1_set
u32 ies_cfg1_set
Definition:
iocfg.h:28
mt8195_iocfg_bm_regs::drv_cfg2
u32 drv_cfg2
Definition:
iocfg.h:15
mt8195_iocfg_bm_regs::reserved5
u32 reserved5[9]
Definition:
iocfg.h:26
mt8195_iocfg_bm_regs::eh_cfg_set
u32 eh_cfg_set
Definition:
iocfg.h:24
mt8195_iocfg_bm_regs::pd_cfg1_clr
u32 pd_cfg1_clr
Definition:
iocfg.h:33
mt8195_iocfg_bm_regs::reserved4
u32 reserved4[1]
Definition:
iocfg.h:22
mt8195_iocfg_bm_regs::smt_cfg0
u32 smt_cfg0
Definition:
iocfg.h:43
mt8195_iocfg_bm_regs::pd_cfg1_set
u32 pd_cfg1_set
Definition:
iocfg.h:32
mt8195_iocfg_bm_regs::drv_cfg1_clr
u32 drv_cfg1_clr
Definition:
iocfg.h:13
mt8195_iocfg_bm_regs::reserved2
u32 reserved2
Definition:
iocfg.h:14
mt8195_iocfg_bm_regs::drv_cfg2_clr
u32 drv_cfg2_clr
Definition:
iocfg.h:17
mt8195_iocfg_bm_regs::pu_cfg1
u32 pu_cfg1
Definition:
iocfg.h:35
mt8195_iocfg_bm_regs::drv_cfg1_set
u32 drv_cfg1_set
Definition:
iocfg.h:12
mt8195_iocfg_bm_regs::eh_cfg_clr
u32 eh_cfg_clr
Definition:
iocfg.h:25
mt8195_iocfg_bm_regs::drv_cfg3_clr
u32 drv_cfg3_clr
Definition:
iocfg.h:21
mt8195_iocfg_bm_regs::pu_cfg1_clr
u32 pu_cfg1_clr
Definition:
iocfg.h:37
src
soc
mediatek
mt8195
include
soc
iocfg.h
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