coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
espi.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
2
3
/*
4
* This file is created based on Intel Alder Lake Processor PCH Datasheet
5
* Document number: 621483
6
* Chapter number: 2
7
*/
8
9
#ifndef _SOC_ALDERLAKE_ESPI_H_
10
#define _SOC_ALDERLAKE_ESPI_H_
11
12
/* PCI Configuration Space (D31:F0): ESPI */
13
#define SCI_IRQ_SEL (7 << 0)
14
#define SCIS_IRQ9 0
15
#define SCIS_IRQ10 1
16
#define SCIS_IRQ11 2
17
#define SCIS_IRQ20 4
18
#define SCIS_IRQ21 5
19
#define SCIS_IRQ22 6
20
#define SCIS_IRQ23 7
21
#define SERIRQ_CNTL 0x64
22
#define ESPI_IO_DEC 0x80
/* IO Decode Ranges Register */
23
#define COMA_RANGE 0x0
/* 0x3F8 - 0x3FF COM1*/
24
#define COMB_RANGE 0x1
/* 0x2F8 - 0x2FF COM2*/
25
#define ESPI_GEN1_DEC 0x84
/* ESPI IF Generic Decode Range 1 */
26
#define ESPI_GEN2_DEC 0x88
/* ESPI IF Generic Decode Range 2 */
27
#define ESPI_GEN3_DEC 0x8c
/* ESPI IF Generic Decode Range 3 */
28
#define ESPI_GEN4_DEC 0x90
/* ESPI IF Generic Decode Range 4 */
29
#define LGMR 0x98
/* ESPI Generic Memory Range */
30
#define PCCTL 0xE0
/* PCI Clock Control */
31
#define CLKRUN_EN (1 << 0)
32
33
#endif
src
soc
intel
alderlake
include
soc
espi.h
Generated by
1.9.1