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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | EPBAR 0x40 |
#define | MCHBAR 0x48 |
#define | GGC 0x50 /* GMCH Graphics Control */ |
#define | DEVEN 0x54 /* Device Enable */ |
#define | DEVEN_D7EN (1 << 14) |
#define | DEVEN_PEG60 (1 << 13) |
#define | DEVEN_D4EN (1 << 7) |
#define | DEVEN_IGD (1 << 4) |
#define | DEVEN_PEG10 (1 << 3) |
#define | DEVEN_PEG11 (1 << 2) |
#define | DEVEN_PEG12 (1 << 1) |
#define | DEVEN_HOST (1 << 0) |
#define | PAVPC 0x58 /* Protected Audio Video Path Control */ |
#define | DPR 0x5c /* DMA Protected Range */ |
#define | PCIEXBAR 0x60 |
#define | DMIBAR 0x68 |
#define | MESEG_BASE 0x70 |
#define | MESEG_MASK 0x78 |
#define | MELCK (1 << 10) /* ME Range Lock */ |
#define | ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ |
#define | PAM0 0x80 |
#define | PAM1 0x81 |
#define | PAM2 0x82 |
#define | PAM3 0x83 |
#define | PAM4 0x84 |
#define | PAM5 0x85 |
#define | PAM6 0x86 |
#define | LAC 0x87 /* Legacy Access Control */ |
#define | SMRAM 0x88 /* System Management RAM Control */ |
#define | REMAPBASE 0x90 |
#define | REMAPLIMIT 0x98 |
#define | TOM 0xa0 |
#define | TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
#define | BDSM 0xb0 /* Base Data of Stolen Memory */ |
#define | BGSM 0xb4 /* Base GTT Stolen Memory */ |
#define | TSEGMB 0xb8 /* TSEG Memory Base */ |
#define | TOLUD 0xbc /* Top of Low Used Memory */ |
#define | CAPID0_A 0xe4 /* Capabilities Register A */ |
#define | CAPID_ECCDIS (1 << 25) |
#define | CAPID_DDPCD (1 << 14) |
#define | CAPID_PDCD (1 << 12) |
#define | CAPID_WRTVREF (1 << 1) |
#define | CAPID_DDRSZ(x) (((x) >> 19) & 0x3) |
#define | CAPID0_B 0xe8 /* Capabilities Register B */ |
#define | SKPAD 0xdc /* Scratchpad Data */ |
#define | DIDOR 0xf3 /* Device ID override, for debug and samples only */ |
#define BDSM 0xb0 /* Base Data of Stolen Memory */ |
Definition at line 46 of file host_bridge.h.
#define BGSM 0xb4 /* Base GTT Stolen Memory */ |
Definition at line 47 of file host_bridge.h.
#define CAPID0_A 0xe4 /* Capabilities Register A */ |
Definition at line 51 of file host_bridge.h.
#define CAPID0_B 0xe8 /* Capabilities Register B */ |
Definition at line 58 of file host_bridge.h.
#define CAPID_DDPCD (1 << 14) |
Definition at line 53 of file host_bridge.h.
Definition at line 56 of file host_bridge.h.
#define CAPID_ECCDIS (1 << 25) |
Definition at line 52 of file host_bridge.h.
#define CAPID_PDCD (1 << 12) |
Definition at line 54 of file host_bridge.h.
#define CAPID_WRTVREF (1 << 1) |
Definition at line 55 of file host_bridge.h.
#define DEVEN 0x54 /* Device Enable */ |
Definition at line 10 of file host_bridge.h.
#define DEVEN_D4EN (1 << 7) |
Definition at line 13 of file host_bridge.h.
#define DEVEN_D7EN (1 << 14) |
Definition at line 11 of file host_bridge.h.
#define DEVEN_HOST (1 << 0) |
Definition at line 18 of file host_bridge.h.
#define DEVEN_IGD (1 << 4) |
Definition at line 14 of file host_bridge.h.
#define DEVEN_PEG10 (1 << 3) |
Definition at line 15 of file host_bridge.h.
#define DEVEN_PEG11 (1 << 2) |
Definition at line 16 of file host_bridge.h.
#define DEVEN_PEG12 (1 << 1) |
Definition at line 17 of file host_bridge.h.
#define DEVEN_PEG60 (1 << 13) |
Definition at line 12 of file host_bridge.h.
#define DIDOR 0xf3 /* Device ID override, for debug and samples only */ |
Definition at line 62 of file host_bridge.h.
#define DMIBAR 0x68 |
Definition at line 24 of file host_bridge.h.
#define DPR 0x5c /* DMA Protected Range */ |
Definition at line 21 of file host_bridge.h.
#define EPBAR 0x40 |
Definition at line 6 of file host_bridge.h.
#define GGC 0x50 /* GMCH Graphics Control */ |
Definition at line 9 of file host_bridge.h.
#define LAC 0x87 /* Legacy Access Control */ |
Definition at line 39 of file host_bridge.h.
#define MCHBAR 0x48 |
Definition at line 7 of file host_bridge.h.
#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */ |
Definition at line 29 of file host_bridge.h.
#define MELCK (1 << 10) /* ME Range Lock */ |
Definition at line 28 of file host_bridge.h.
#define MESEG_BASE 0x70 |
Definition at line 26 of file host_bridge.h.
#define MESEG_MASK 0x78 |
Definition at line 27 of file host_bridge.h.
#define PAM0 0x80 |
Definition at line 31 of file host_bridge.h.
#define PAM1 0x81 |
Definition at line 32 of file host_bridge.h.
#define PAM2 0x82 |
Definition at line 33 of file host_bridge.h.
#define PAM3 0x83 |
Definition at line 34 of file host_bridge.h.
#define PAM4 0x84 |
Definition at line 35 of file host_bridge.h.
#define PAM5 0x85 |
Definition at line 36 of file host_bridge.h.
#define PAM6 0x86 |
Definition at line 37 of file host_bridge.h.
#define PAVPC 0x58 /* Protected Audio Video Path Control */ |
Definition at line 20 of file host_bridge.h.
#define PCIEXBAR 0x60 |
Definition at line 23 of file host_bridge.h.
#define REMAPBASE 0x90 |
Definition at line 42 of file host_bridge.h.
#define REMAPLIMIT 0x98 |
Definition at line 43 of file host_bridge.h.
#define SKPAD 0xdc /* Scratchpad Data */ |
Definition at line 60 of file host_bridge.h.
#define SMRAM 0x88 /* System Management RAM Control */ |
Definition at line 40 of file host_bridge.h.
#define TOLUD 0xbc /* Top of Low Used Memory */ |
Definition at line 49 of file host_bridge.h.
#define TOM 0xa0 |
Definition at line 44 of file host_bridge.h.
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ |
Definition at line 45 of file host_bridge.h.
#define TSEGMB 0xb8 /* TSEG Memory Base */ |
Definition at line 48 of file host_bridge.h.