coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
w83627ehg.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef SUPERIO_WINBOND_W83627EHG_H
4 #define SUPERIO_WINBOND_W83627EHG_H
5 
6 #define W83627EHG_FDC 0 /* Floppy */
7 #define W83627EHG_PP 1 /* Parallel port */
8 #define W83627EHG_SP1 2 /* Com1 */
9 #define W83627EHG_SP2 3 /* Com2 */
10 #define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */
11 #define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */
12 #define W83627EHG_ACPI 10 /* ACPI */
13 #define W83627EHG_HWM 11 /* Hardware monitor */
14 
15 /* The following are handled using "virtual LDNs" (hence the _V suffix). */
16 #define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */
17 #define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */
18 #define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
19 
20 /*
21  * Virtual devices sharing the enables are encoded as follows:
22  * VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
23  */
24 
25 /* SFI has bit 1 as enable (instead of bit 0 as usual). */
26 #define W83627EHG_SFI ((1 << 8) | W83627EHG_SFI_V)
27 
28 #define W83627EHG_GPIO1 ((0 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
29 #define W83627EHG_GAME ((1 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
30 #define W83627EHG_MIDI ((2 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
31 #define W83627EHG_GPIO6 ((3 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
32 
33 #define W83627EHG_GPIO2 ((0 << 8) | W83627EHG_GPIO_SUSLED_V)
34 #define W83627EHG_GPIO3 ((1 << 8) | W83627EHG_GPIO_SUSLED_V)
35 #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V)
36 #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V)
37 
38 #endif /* SUPERIO_WINBOND_W83627EHG_H */