coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
spi.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _BAYTRAIL_SPI_H_
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#define _BAYTRAIL_SPI_H_
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#include <
stdint.h
>
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/* These registers live behind SPI_BASE_ADDRESS. */
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#define HSFSTS 0x04
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# define FLOCKDN (0x1 << 15)
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#define PREOP 0x94
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#define OPTYPE 0x96
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#define OPMENU0 0x98
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#define OPMENU1 0x9c
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#define LVSCC 0xc4
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# define VCL (0x1 << 23)
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# define EO(x) (((x) & 0xff) << 8)
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# define WG_1_BYTE (0x0 << 2)
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# define WG_64_BYTE (0x1 << 2)
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# define BES_256_BYTE (0x0 << 0)
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# define BES_4_KB (0x1 << 0)
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# define BES_8_KB (0x2 << 0)
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# define BES_64_KB (0x3 << 0)
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#define UVSCC 0xc8
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#define SCS 0xf8
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# define SMIWPEN (0x1 << 7)
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#define BCR 0xfc
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# define EISS (0x1 << 5)
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# define SRC_MASK (0x3 << 2)
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# define SRC_CACHE_NO_PREFETCH (0x0 << 2)
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# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2)
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# define SRC_CACHE_PREFETCH (0x2 << 2)
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# define BCR_LE (0x1 << 1)
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# define BCR_WPD (0x1 << 0)
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/*
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* SPI lockdown configuration.
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*/
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struct
spi_config
{
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uint16_t
preop
;
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uint16_t
optype
;
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uint32_t
opmenu
[2];
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uint32_t
lvscc
;
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uint32_t
uvscc
;
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};
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/* Return 0 on success < 0 on failure. */
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int
mainboard_get_spi_config
(
struct
spi_config
*cfg);
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#endif
/* _BAYTRAIL_SPI_H_ */
mainboard_get_spi_config
int mainboard_get_spi_config(struct spi_config *cfg)
Definition:
w25q64.c:52
stdint.h
uint16_t
unsigned short uint16_t
Definition:
stdint.h:11
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
spi_config
Definition:
spi.h:77
spi_config::preop
uint16_t preop
Definition:
spi.h:40
spi_config::opmenu
uint32_t opmenu[2]
Definition:
spi.h:42
spi_config::optype
uint16_t optype
Definition:
spi.h:41
spi_config::lvscc
uint32_t lvscc
Definition:
spi.h:43
spi_config::uvscc
uint32_t uvscc
Definition:
spi.h:44
src
soc
intel
baytrail
include
soc
spi.h
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