coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
spi.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _BAYTRAIL_SPI_H_
4 #define _BAYTRAIL_SPI_H_
5 
6 #include <stdint.h>
7 
8 /* These registers live behind SPI_BASE_ADDRESS. */
9 #define HSFSTS 0x04
10 # define FLOCKDN (0x1 << 15)
11 #define PREOP 0x94
12 #define OPTYPE 0x96
13 #define OPMENU0 0x98
14 #define OPMENU1 0x9c
15 #define LVSCC 0xc4
16 # define VCL (0x1 << 23)
17 # define EO(x) (((x) & 0xff) << 8)
18 # define WG_1_BYTE (0x0 << 2)
19 # define WG_64_BYTE (0x1 << 2)
20 # define BES_256_BYTE (0x0 << 0)
21 # define BES_4_KB (0x1 << 0)
22 # define BES_8_KB (0x2 << 0)
23 # define BES_64_KB (0x3 << 0)
24 #define UVSCC 0xc8
25 #define SCS 0xf8
26 # define SMIWPEN (0x1 << 7)
27 #define BCR 0xfc
28 # define EISS (0x1 << 5)
29 # define SRC_MASK (0x3 << 2)
30 # define SRC_CACHE_NO_PREFETCH (0x0 << 2)
31 # define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2)
32 # define SRC_CACHE_PREFETCH (0x2 << 2)
33 # define BCR_LE (0x1 << 1)
34 # define BCR_WPD (0x1 << 0)
35 
36 /*
37  * SPI lockdown configuration.
38  */
39 struct spi_config {
45 };
46 
47 /* Return 0 on success < 0 on failure. */
48 int mainboard_get_spi_config(struct spi_config *cfg);
49 
50 #endif /* _BAYTRAIL_SPI_H_ */
int mainboard_get_spi_config(struct spi_config *cfg)
Definition: w25q64.c:52
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
Definition: spi.h:77
uint16_t preop
Definition: spi.h:40
uint32_t opmenu[2]
Definition: spi.h:42
uint16_t optype
Definition: spi.h:41
uint32_t lvscc
Definition: spi.h:43
uint32_t uvscc
Definition: spi.h:44