coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/gpio.h>
4 #include "gpio.h"
5 
6 /*
7  * As a rule of thumb, GPIO pins used by coreboot should be initialized at
8  * bootblock while GPIO pins used only by the OS should be initialized at
9  * ramstage.
10  */
11 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
12  /* I2S SDIN */
13  PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
14  /* I2S LRCLK */
15  PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
16  /* not Blink */
18  /* APU_ALS_INT# */
19  PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
20  /* NFC IRQ */
21  PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
22 };
23 
25 {
27 }
#define GPIO_11
Definition: gpio_ftns.h:13
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define PULL_UP
Definition: buildOpts.c:70
#define PULL_NONE
Definition: buildOpts.c:72
void mainboard_program_gpios(void)
Definition: gpio.c:24
static const struct soc_amd_gpio gpio_set_stage_ram[]
Definition: gpio.c:11
#define GPIO_7
Definition: gpio.h:28
#define GPIO_69
Definition: gpio.h:55
#define GPIO_8
Definition: gpio.h:29
#define GPIO_24
Definition: gpio.h:42
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307
#define PAD_SCI(pin, pull, trigger)
Definition: gpio_defs.h:229
#define PAD_NF(pin, func, pull)
Definition: gpio_defs.h:208
#define PAD_INT(pin, pull, trigger, action)
Definition: gpio_defs.h:224
#define PAD_GPI(pin, pull)
Definition: gpio_defs.h:216