coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
arch/romstage.h
>
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#include <
intelblocks/rtc.h
>
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#include <
console/console.h
>
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#include <
cpu/x86/mtrr.h
>
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#include <fsp/util.h>
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#include <soc/romstage.h>
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#include <
soc/util.h
>
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void
mainboard_romstage_entry
(
void
)
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{
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rtc_init
();
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if
(
soc_get_rtc_failed
())
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mainboard_rtc_failed
();
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fsp_memory_init
(
false
);
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printk
(
BIOS_DEBUG
,
"coreboot fsp_memory_init finished...\n"
);
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unlock_pam_regions
();
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save_dimm_info
();
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}
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__weak
void
mainboard_memory_init_params
(FSPM_UPD *mupd)
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{
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printk
(
BIOS_SPEW
,
"WARNING: using default FSP-M parameters!\n"
);
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}
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__weak
void
mainboard_rtc_failed
(
void
)
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{
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}
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__weak
void
save_dimm_info
(
void
) { }
romstage.h
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
fsp_memory_init
void fsp_memory_init(bool s3wake)
Definition:
memory_init.c:350
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
BIOS_SPEW
#define BIOS_SPEW
BIOS_SPEW - Excessively verbose output.
Definition:
loglevel.h:142
mainboard_memory_init_params
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition:
romstage.c:22
mainboard_romstage_entry
void mainboard_romstage_entry(void)
Definition:
romstage.c:6
mainboard_rtc_failed
void mainboard_rtc_failed(void)
Definition:
romstage.c:209
__weak
const struct smm_save_state_ops *legacy_ops __weak
Definition:
save_state.c:8
soc_get_rtc_failed
int soc_get_rtc_failed(void)
Definition:
pmutil.c:174
rtc.h
rtc_init
void rtc_init(void)
Definition:
rtc.c:29
save_dimm_info
void save_dimm_info(void)
Definition:
romstage.c:78
util.h
unlock_pam_regions
void unlock_pam_regions(void)
Definition:
util.c:27
mtrr.h
src
soc
intel
xeon_sp
romstage.c
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