coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
superio.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /* RAM driver for the SMSC LPC47M15X Super I/O chip */
4 
5 #include <device/device.h>
6 #include <device/pnp.h>
7 #include <superio/conf_mode.h>
8 #include <pc80/keyboard.h>
9 
10 #include "lpc47m15x.h"
11 
12 /* Forward declarations */
13 static void enable_dev(struct device *dev);
14 static void lpc47m15x_init(struct device *dev);
15 
17  CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O")
18  .enable_dev = enable_dev
19 };
20 
21 static struct device_operations ops = {
23  .set_resources = pnp_set_resources,
24  .enable_resources = pnp_enable_resources,
25  .enable = pnp_alt_enable,
26  .init = lpc47m15x_init,
27  .ops_pnp_mode = &pnp_conf_mode_55_aa,
28 };
29 
30 static struct pnp_info pnp_dev_info[] = {
31  { NULL, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
32  { NULL, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
33  { NULL, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
34  { NULL, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
36  0x07ff, 0x07ff, },
37 };
38 
39 static void enable_dev(struct device *dev)
40 {
42 }
43 
44 static void lpc47m15x_init(struct device *dev)
45 {
46 
47  if (!dev->enabled)
48  return;
49 
50  switch (dev->path.pnp.device) {
51  case LPC47M15X_KBC:
53  break;
54  }
55 }
#define ARRAY_SIZE(a)
Definition: helpers.h:12
const struct pnp_mode_ops pnp_conf_mode_55_aa
Definition: conf_mode.c:175
#define CHIP_NAME(X)
Definition: device.h:32
uint8_t pc_keyboard_init(uint8_t probe_aux)
Definition: keyboard.c:229
#define NO_AUX_DEVICE
Definition: keyboard.h:6
#define LPC47M15X_KBC
Definition: lpc47m15x.h:10
#define LPC47M15X_PP
Definition: lpc47m15x.h:7
#define LPC47M15X_FDC
Definition: lpc47m15x.h:6
#define LPC47M15X_SP1
Definition: lpc47m15x.h:8
#define LPC47M15X_SP2
Definition: lpc47m15x.h:9
#define PNP_IRQ1
Definition: pnp.h:48
#define PNP_DRQ0
Definition: pnp.h:49
#define PNP_IO1
Definition: pnp.h:43
#define PNP_IO0
Definition: pnp.h:42
#define PNP_IRQ0
Definition: pnp.h:47
void pnp_read_resources(struct device *dev)
Definition: pnp_device.c:114
void pnp_enable_devices(struct device *base_dev, struct device_operations *ops, unsigned int functions, struct pnp_info *info)
Definition: pnp_device.c:371
void pnp_set_resources(struct device *dev)
Definition: pnp_device.c:157
void pnp_alt_enable(struct device *dev)
Definition: pnp_device.c:191
void pnp_enable_resources(struct device *dev)
Definition: pnp_device.c:173
static void enable_dev(struct device *dev)
Definition: superio.c:39
static struct device_operations ops
Definition: superio.c:21
static struct pnp_info pnp_dev_info[]
Definition: superio.c:30
static void lpc47m15x_init(struct device *dev)
Definition: superio.c:44
struct chip_operations superio_smsc_lpc47m15x_ops
Definition: superio.c:16
#define NULL
Definition: stddef.h:19
void(* read_resources)(struct device *dev)
Definition: device.h:39
struct pnp_path pnp
Definition: path.h:117
Definition: device.h:107
struct device_path path
Definition: device.h:115
unsigned int enabled
Definition: device.h:122
Definition: pnp.h:37
unsigned int device
Definition: path.h:59