6 #define PERIPH_BLK_BLSP 1
8 #define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
9 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
37 #define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
38 (MSM_BOOT_UART_DM_SBL_1 << 2) | \
39 (MSM_BOOT_UART_DM_8_BPS << 4))
44 #define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
45 #define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
46 #define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
47 #define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
51 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
53 #define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
58 #define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x)))
60 #define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
65 #define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
67 #define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
69 #define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
70 #define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
71 #define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
72 #define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
75 #define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
76 #define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4) << 11)
77 #define MSM_BOOT_UART_DM_CR_CH_CMD(x) \
78 (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
79 #define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
80 #define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
81 #define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
82 #define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
83 #define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
84 #define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
85 #define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
86 #define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
87 #define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
88 #define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
89 #define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
90 #define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
91 #define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
92 #define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
93 #define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
94 #define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
95 #define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
96 #define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
99 #define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
101 #define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
102 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
103 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
104 #define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
105 #define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
106 #define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
107 #define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
111 #define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
113 #define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
116 #define MSM_BOOT_UART_DM_TXLEV (1 << 0)
117 #define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
118 #define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
119 #define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
120 #define MSM_BOOT_UART_DM_RXLEV (1 << 4)
121 #define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
122 #define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
123 #define MSM_BOOT_UART_DM_TX_READY (1 << 7)
124 #define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
125 #define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
126 #define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
127 #define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
128 #define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
130 #define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
131 MSM_BOOT_UART_DM_TXLEV | \
132 MSM_BOOT_UART_DM_RXSTALE)
135 #define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
136 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
137 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0
140 #define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
142 #define MSM_BOOT_UART_DM_TFW_VALUE 0
144 #define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
146 #define MSM_BOOT_UART_DM_RFW_VALUE 0
149 #define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
152 #define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
155 #define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
159 #define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
161 #define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
165 #define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
168 #define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
171 #define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
175 #define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
177 #define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
179 #define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
180 #define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
181 #define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
182 #define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
183 #define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
184 #define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
185 #define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
186 #define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
187 #define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
191 #define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
193 #define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
198 #define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
200 #define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
205 #define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
207 #define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
212 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
214 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
218 #define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
219 #define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
220 #define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) \
221 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
222 #define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
223 #define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \
224 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
227 #define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
228 #define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
229 #define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) \
230 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
231 #define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
232 #define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \
233 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
236 #define MSM_BOOT_UART_DM_E_SUCCESS 0
237 #define MSM_BOOT_UART_DM_E_FAILURE 1
238 #define MSM_BOOT_UART_DM_E_TIMEOUT 2
239 #define MSM_BOOT_UART_DM_E_INVAL 3
240 #define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
241 #define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
MSM_BOOT_UART_DM_BITS_PER_CHAR
MSM_BOOT_UART_DM_PARITY_MODE
MSM_BOOT_UART_DM_STOP_BIT_LEN
void qcs405_uart_init(void)
void __udelay(unsigned long usec)
@ MSM_BOOT_UART_DM_NO_PARITY
@ MSM_BOOT_UART_DM_EVEN_PARITY
@ MSM_BOOT_UART_DM_SPACE_PARITY
@ MSM_BOOT_UART_DM_ODD_PARITY
@ MSM_BOOT_UART_DM_SBL_1_9_16
@ MSM_BOOT_UART_DM_SBL_9_16