#include <types.h>

Include dependency graph for dramc_register.h:

Data Structures
struct	dramc_ao_regs

struct	dramc_nao_regs

struct	dramc_ddrphy_regs

struct	emi_regs

struct	dramc_channel

Macros
#define	DRIVING_DS2_0 7 /* DS[2:0] 7->6 */

#define	DEFAULT_DRIVING 0x99009900

Enumerations
enum	{ CONF2_TEST1_EN = BIT(29) , CONF2_TEST2R_EN = BIT(30) , CONF2_TEST2W_EN = BIT(31) , PADCTL1_CLK_SHIFT = 24 , PADCTL1_CS1_SHIFT = 28 , MASK_PADCTL2_16BIT = 0x000000ff , MASK_PADCTL2_32BIT = 0x0000ffff , MASK_PADCTL2 = 0xffff0000 , PADCTL2_SHIFT = 0 , TEST2_3_TESTCNT_SHIFT = 0 , TEST2_3_TESTCNT_MASK = (0xful << TEST2_3_TESTCNT_SHIFT) , TEST2_3_TESTAUDPAT_EN = BIT(7) , TEST2_3_ADVREFEN_EN = BIT(30) , TEST2_4_TESTAUDINC_SHIFT = 0 , TEST2_4_TESTAUDINC_MASK = (0x1ful << TEST2_4_TESTAUDINC_SHIFT) , TEST2_4_TESTAUDINIT_SHIFT = 8 , TEST2_4_TESTAUDINIT_MASK = (0x1ful << TEST2_4_TESTAUDINIT_SHIFT) , TEST2_4_TESTAUDBITINV_EN = BIT(14) , TEST2_4_TESTAUDMODE_EN = BIT(15) , TEST2_4_TESTXTALKPAT_EN = BIT(16) , DDR2CTL_WOEN_SHIFT = 3 , DDR2CTL_DATLAT_SHIFT = 4 , MISC_LATNORMP_SHIFT = 0 , MISC_DATLAT_DSEL_SHIFT = 8 , MASK_MR2_OP = 0x00800000 , DQSIEN_DQS0IEN_SHIFT = 0 , DQSIEN_DQS1IEN_SHIFT = 8 , DQSIEN_DQS2IEN_SHIFT = 16 , DQSIEN_DQS3IEN_SHIFT = 24 , MCKDLY_DQIENLAT_SHIFT = 4 , MCKDLY_DQIENQKEND_SHIFT = 10 , MCKDLY_FIXDQIEN_SHIFT = 12 , MCKDLY_FIXODT_SHIFT = 23 , DQSCTL1_DQSINCTL_SHIFT = 24 , DQSCTL1_DQSIENMODE_SHIFT = 28 , PADCTL4_CKEFIXON_SHIFT = 2 , PADCTL4_DATLAT3_SHIFT = 4 , PHYCTL1_DATLAT4_SHIFT = 25 , PHYCTL1_PHYRST_SHIFT = 28 , GDDR3CTL1_BKSWAP_SHIFT = 20 , GDDR3CTL1_RDATRST_SHIFT = 25 , GDDR3CTL1_DQMSWAP_SHIFT = 31 , MASK_RKCFG_RKSWAP_EN = 0x08 , RKCFG_PBREF_DISBYRATE_SHIFT = 6 , RKCFG_WDATKEY64_SHIFT = 29 , DQSCTL2_DQSINCTL_SHIFT = 0 , DQSGCTL_DQSGDUALP_SHIFT = 30 , PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT = 16 , PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT = 18 , PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT = 28 , CMDDLY0_RA0_SHIFT = 0 , CMDDLY0_RA1_SHIFT = 8 , CMDDLY0_RA2_SHIFT = 16 , CMDDLY0_RA3_SHIFT = 24 , CMDDLY1_RA7_SHIFT = 24 , CMDDLY3_BA0_SHIFT = 8 , CMDDLY3_BA1_SHIFT = 16 , CMDDLY3_BA2_SHIFT = 24 , CMDDLY4_CS_SHIFT = 0 , CMDDLY4_CKE_SHIFT = 8 , CMDDLY4_RAS_SHIFT = 16 , CMDDLY4_CAS_SHIFT = 24 , CMDDLY5_WE_SHIFT = 8 , CMDDLY5_RA13_SHIFT = 16 , DQSCAL0_RA14_SHIFT = 24 , DQSCAL0_STBCALEN_SHIFT = 31 , DQSCAL1_CKE1_SHIFT = 24 , IMP_CALI_EN_SHIFT = 0 , IMP_CALI_HW_SHIFT = 1 , IMP_CALI_ENN_SHIFT = 4 , IMP_CALI_ENP_SHIFT = 5 , IMP_CALI_PDN_SHIFT = 6 , IMP_CALI_PDP_SHIFT = 7 , IMP_CALI_DRVP_SHIFT = 8 , IMP_CALI_DRVN_SHIFT = 12 , JMETER_EN_BIT = BIT(0) , JMETER_COUNTER_SHIFT = 16 , JMETER_COUNTER_MASK = (0xffff << JMETER_COUNTER_SHIFT) , SPCMD_MRWEN_SHIFT = 0 , SPCMD_DQSGCNTEN_SHIFT = 8 , SPCMD_DQSGCNTRST_SHIFT = 9 , JMETER_PLL_ZERO_SHIFT = 0 , JMETER_PLL_ONE_SHIFT = 16 , TESTRPT_DM_CMP_CPT_SHIFT = 10 , TESTRPT_DM_CMP_ERR_SHIFT = 14 , SELPH2_TXDLY_DQSGATE_SHIFT = 12 , SELPH2_TXDLY_DQSGATE_P1_SHIFT = 20 , SELPH5_DLY_DQSGATE_SHIFT = 22 , SELPH5_DLY_DQSGATE_P1_SHIFT = 24 , SELPH6_1_DLY_R1DQSGATE_SHIFT = 0 , SELPH6_1_DLY_R1DQSGATE_P1_SHIFT = 2 , SELPH6_1_TXDLY_R1DQSGATE_SHIFT = 4 , SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT = 8 , MASK_MEMPLL_DL = 0xc0ffffff , MEMPLL_FB_DL_SHIFT = 0 , MEMPLL_REF_DL_SHIFT = 8 , MEMPLL_DL_SHIFT = 24 , MEMPLL_MODE_SHIFT = 29 , MEMCLKENB_SHIFT = 5 }

Functions
	check_member (dramc_ao_regs, selph11, 0x42c)

	check_member (dramc_nao_regs, testrpt, 0x3fc)

	check_member (dramc_ddrphy_regs, mempll05_divider, 0x690)

	check_member (emi_regs, emi_bmen, 0x400)

Variables
struct dramc_ao_regs *	ao_regs

struct dramc_nao_regs *	nao_regs

struct dramc_ddrphy_regs *	ddrphy_regs

static struct dramc_channel const	ch [2]

Macro Definition Documentation

◆ DEFAULT_DRIVING

#define DEFAULT_DRIVING 0x99009900

Definition at line 9 of file dramc_register.h.

◆ DRIVING_DS2_0

#define DRIVING_DS2_0 7 /* DS[2:0] 7->6 */

Definition at line 8 of file dramc_register.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
CONF2_TEST1_EN
CONF2_TEST2R_EN
CONF2_TEST2W_EN
PADCTL1_CLK_SHIFT
PADCTL1_CS1_SHIFT
MASK_PADCTL2_16BIT
MASK_PADCTL2_32BIT
MASK_PADCTL2
PADCTL2_SHIFT
TEST2_3_TESTCNT_SHIFT
TEST2_3_TESTCNT_MASK
TEST2_3_TESTAUDPAT_EN
TEST2_3_ADVREFEN_EN
TEST2_4_TESTAUDINC_SHIFT
TEST2_4_TESTAUDINC_MASK
TEST2_4_TESTAUDINIT_SHIFT
TEST2_4_TESTAUDINIT_MASK
TEST2_4_TESTAUDBITINV_EN
TEST2_4_TESTAUDMODE_EN
TEST2_4_TESTXTALKPAT_EN
DDR2CTL_WOEN_SHIFT
DDR2CTL_DATLAT_SHIFT
MISC_LATNORMP_SHIFT
MISC_DATLAT_DSEL_SHIFT
MASK_MR2_OP
DQSIEN_DQS0IEN_SHIFT
DQSIEN_DQS1IEN_SHIFT
DQSIEN_DQS2IEN_SHIFT
DQSIEN_DQS3IEN_SHIFT
MCKDLY_DQIENLAT_SHIFT
MCKDLY_DQIENQKEND_SHIFT
MCKDLY_FIXDQIEN_SHIFT
MCKDLY_FIXODT_SHIFT
DQSCTL1_DQSINCTL_SHIFT
DQSCTL1_DQSIENMODE_SHIFT
PADCTL4_CKEFIXON_SHIFT
PADCTL4_DATLAT3_SHIFT
PHYCTL1_DATLAT4_SHIFT
PHYCTL1_PHYRST_SHIFT
GDDR3CTL1_BKSWAP_SHIFT
GDDR3CTL1_RDATRST_SHIFT
GDDR3CTL1_DQMSWAP_SHIFT
MASK_RKCFG_RKSWAP_EN
RKCFG_PBREF_DISBYRATE_SHIFT
RKCFG_WDATKEY64_SHIFT
DQSCTL2_DQSINCTL_SHIFT
DQSGCTL_DQSGDUALP_SHIFT
PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT
PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT
PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT
CMDDLY0_RA0_SHIFT
CMDDLY0_RA1_SHIFT
CMDDLY0_RA2_SHIFT
CMDDLY0_RA3_SHIFT
CMDDLY1_RA7_SHIFT
CMDDLY3_BA0_SHIFT
CMDDLY3_BA1_SHIFT
CMDDLY3_BA2_SHIFT
CMDDLY4_CS_SHIFT
CMDDLY4_CKE_SHIFT
CMDDLY4_RAS_SHIFT
CMDDLY4_CAS_SHIFT
CMDDLY5_WE_SHIFT
CMDDLY5_RA13_SHIFT
DQSCAL0_RA14_SHIFT
DQSCAL0_STBCALEN_SHIFT
DQSCAL1_CKE1_SHIFT
IMP_CALI_EN_SHIFT
IMP_CALI_HW_SHIFT
IMP_CALI_ENN_SHIFT
IMP_CALI_ENP_SHIFT
IMP_CALI_PDN_SHIFT
IMP_CALI_PDP_SHIFT
IMP_CALI_DRVP_SHIFT
IMP_CALI_DRVN_SHIFT
JMETER_EN_BIT
JMETER_COUNTER_SHIFT
JMETER_COUNTER_MASK
SPCMD_MRWEN_SHIFT
SPCMD_DQSGCNTEN_SHIFT
SPCMD_DQSGCNTRST_SHIFT
JMETER_PLL_ZERO_SHIFT
JMETER_PLL_ONE_SHIFT
TESTRPT_DM_CMP_CPT_SHIFT
TESTRPT_DM_CMP_ERR_SHIFT
SELPH2_TXDLY_DQSGATE_SHIFT
SELPH2_TXDLY_DQSGATE_P1_SHIFT
SELPH5_DLY_DQSGATE_SHIFT
SELPH5_DLY_DQSGATE_P1_SHIFT
SELPH6_1_DLY_R1DQSGATE_SHIFT
SELPH6_1_DLY_R1DQSGATE_P1_SHIFT
SELPH6_1_TXDLY_R1DQSGATE_SHIFT
SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT
MASK_MEMPLL_DL
MEMPLL_FB_DL_SHIFT
MEMPLL_REF_DL_SHIFT
MEMPLL_DL_SHIFT
MEMPLL_MODE_SHIFT
MEMCLKENB_SHIFT

Definition at line 11 of file dramc_register.h.

Function Documentation

◆ check_member() [1/4]

check_member	(	dramc_ao_regs	,
		selph11	,
		0x42c
	)

◆ check_member() [2/4]

check_member	(	dramc_ddrphy_regs	,
		mempll05_divider	,
		0x690
	)

◆ check_member() [3/4]

check_member	(	dramc_nao_regs	,
		testrpt	,
		0x3fc
	)

◆ check_member() [4/4]

check_member	(	emi_regs	,
		emi_bmen	,
		0x400
	)

Variable Documentation

◆ ao_regs

◆ ch

struct dramc_channel const ch[2]

static

Initial value:

= {
        {(void *)CHA_DRAMCAO_BASE, (void *)CHA_DRAMCNAO_BASE, (void *)CHA_DDRPHY_BASE},
        {(void *)CHB_DRAMCAO_BASE, (void *)CHB_DRAMCNAO_BASE, (void *)CHB_DDRPHY_BASE}
}

Definition at line 495 of file dramc_register.h.

Referenced by ast_is_vga_enabled(), auto_refresh_cke_off(), ca_training(), cbt_dramc_dfs_direct_jump(), cbt_entry(), cbt_exit(), cbt_mrr_pinmux_mapping(), cbt_set_ca_clk_result(), cbt_set_perbit_delay_cell(), cbt_set_vref(), clk_duty_cal(), clkset0(), clkset1(), clock_crossing_setup(), cmdset(), configure_dram_control_mode(), ctrlset0(), ctrlset1(), ctrlset2(), ctrlset3(), ddr3_read_io_init(), ddr3_select_clock_mux(), ddr3_write_io_init(), ddr5_fill_dimm_module_info(), ddr_phy_pll_setting(), ddr_phy_reserved_rg_setting(), ddr_update_ac_timing(), div2_phase_sync(), dl_oem_smbios_strings(), do_raminit(), dqs_gw_counter_reset(), dqs_gw_test(), dqset(), dqsosc_auto(), dqsosc_shu_settings(), dqsset(), dram_optimizations(), dram_phy_reset(), dram_program_banks(), dramc_ac_timing_optimize(), dramc_apply_config_after_calibration(), dramc_apply_config_before_calibration(), dramc_auto_refresh_switch(), dramc_cke_fix_onoff(), dramc_cmd_bus_training(), dramc_dle_factor_handler(), dramc_dqs_precalculation_preset(), dramc_dummy_read_for_tracking_enable(), dramc_duty_set_clk_delay(), dramc_duty_set_dqs_delay(), dramc_enable_dramc_dcm(), dramc_enable_phy_dcm(), dramc_engine2(), dramc_engine2_check_complete(), dramc_engine2_compare(), dramc_engine2_end(), dramc_engine2_init(), dramc_engine2_run(), dramc_engine2_setpat(), dramc_find_dly_tune(), dramc_gating_mode(), dramc_get_smallest_dqs_dly(), dramc_hw_dqs_gating_tracking(), dramc_hw_dqsosc(), dramc_hw_gating_init(), dramc_hw_gating_onoff(), dramc_impedance_tracking_enable(), dramc_init(), dramc_init_pre_settings(), dramc_mode_reg_init(), dramc_mode_reg_read(), dramc_mode_reg_read_by_rank(), dramc_mode_reg_write(), dramc_mode_reg_write_by_rank(), dramc_pa_improve(), dramc_phy_dcm_2_channel(), dramc_phy_low_power_enable(), dramc_phy_reset(), dramc_power_on_sequence(), dramc_pre_init(), dramc_rankinctl_config(), dramc_read_dbi_onoff(), dramc_reset_delay_chain_before_calibration(), dramc_runtime_config(), dramc_rx_datlat_cal(), dramc_rx_dqs_gating_cal(), dramc_rx_dqs_gating_cal_partial(), dramc_rx_dqs_gating_cal_pre(), dramc_rx_dqs_gating_post_process(), dramc_rx_dqs_isi_pulse_cg_switch(), dramc_rx_input_delay_tracking(), dramc_rx_input_delay_tracking_init_by_freq(), dramc_rx_rd_dqc_end(), dramc_rx_rd_dqc_init(), dramc_rx_rd_dqc_run(), dramc_rx_vref_pre_setting(), dramc_save_result_to_shuffle(), dramc_set_CKE_2_rank_independent(), dramc_set_gating_mode(), dramc_set_mr13_vrcg_to_normal(), dramc_set_rank_engine2(), dramc_set_rx_best_dly_factor(), dramc_set_rx_dly_factor(), dramc_set_rx_vref(), dramc_set_tx_best_dly_factor(), dramc_set_tx_dly_factor(), dramc_setting_DDR1600(), dramc_setting_DDR2400(), dramc_setting_DDR3600(), dramc_sw_imp_cal_vref_sel(), dramc_sw_impedance_cal(), dramc_sw_impedance_save_reg(), dramc_window_perbit_cal(), dramc_write_dbi_onoff(), dramc_write_dqs_gating_result(), dramc_write_leveling(), dramc_zq_calibration(), dual_rank_rx_datlat_cal(), dual_rank_rx_dqs_gating_cal(), dvfs_settings(), emi_esl_setting1(), emi_esl_setting2(), emi_init(), gm45_early_reset(), iosav_run_once_and_wait(), iosav_run_queue(), iosav_write_sequence(), jedec_ddr2(), jedec_ddr3(), jedec_init(), make_channel_disabled_mask(), mem_init_spd_upds(), mem_pll_init(), mem_pll_init_phase_sync(), mem_pll_init_set_params(), mem_pll_phase_cali(), mem_pll_pre_init(), move_dramc_tx_dq(), move_dramc_tx_dq_oen(), move_dramc_tx_dqs(), move_dramc_tx_dqs_oen(), mrs_write(), o1_path_on_off(), odt_setup(), perform_read_training(), perform_write_training(), pll_phase_adjust(), pll_phase_check(), power_settings(), program_memory_map(), program_read_timing(), program_write_timing(), raminit(), raminit_receive_enable_calibration(), rank_is_populated(), read_spd_dimm(), read_spd_md(), read_training_restore_results(), read_training_store_results(), receive_enable_calibration(), rkclk_ddr_phy_ctl_reset(), rkclk_ddr_reset(), rx_datlat_cal(), rx_dqs_gating_cal(), save_dimm_info(), sdram_dradrb(), sdram_enhancedmode(), sdram_jedecinit(), sdram_size_mb(), sdram_timings(), search_write_leveling(), select_default_dq_dqs_settings(), send_jedec_cmd(), set_all_dq_dqs_dll_settings(), set_dle_factor(), set_dradrb(), set_dram_mr_cbt_on_off(), set_enhanced_mode(), set_gw_coarse_factor(), set_gw_coarse_factor_rank1(), set_gw_fine_factor(), set_mrr_pinmux_mapping(), set_rank_info_to_conf(), set_rx_best_dly_factor(), set_rx_dly_factor(), set_tx_best_dly_factor(), set_tx_dly_factor(), setup_sdram_meminfo(), start_dqsosc(), sw_impedance_cal(), transfer_pll_to_spm_control(), transfer_to_reg_control(), transfer_to_spm_control(), update_initial_settings(), variant_board_sku(), write_leveling(), write_training_find_lower(), write_training_find_upper(), write_training_per_group(), write_training_restore_results(), write_training_store_results(), and write_txdll_tap_pi().

◆ ddrphy_regs

◆ nao_regs

struct dramc_nao_regs* nao_regs

extern

Referenced by dqs_gw_test(), and dramc_engine2().

Data Structures

Macros

Enumerations

Functions

Variables