coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
memory.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <baseboard/gpio.h>
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#include <gpio.h>
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#include <
soc/cnl_memcfg_init.h
>
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#include <
string.h
>
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#include <variant/gpio.h>
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static
const
struct
cnl_mb_cfg
baseboard_memcfg
= {
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/*
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* The dqs_map arrays map the SoC pins to the lpddr3 pins
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* for both channels.
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*
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* "The index of the array is CPU byte number, the values are DRAM byte
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* numbers." - doc #573387
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*
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* the index = pin number on SoC
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* the value = pin number on lpddr3 part
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*/
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.
dqs_map
[
DDR_CH0
] = {4, 7, 5, 6, 0, 3, 2, 1},
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.dqs_map[
DDR_CH1
] = {0, 3, 2, 1, 4, 7, 6, 5},
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.dq_map[
DDR_CH0
] = {
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{0xf0, 0xf},
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{0x0, 0xf},
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{0xf0, 0xf},
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{0xf0, 0x0},
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{0xff, 0x0},
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{0xff, 0x0}
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},
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.dq_map[
DDR_CH1
] = {
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{0xf, 0xf0},
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{0x0, 0xf0},
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{0xf, 0xf0},
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{0xf, 0x0},
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{0xff, 0x0},
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{0xff, 0x0}
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},
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/* Palkia uses 200, 80.6 and 162 rcomp resistors */
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.rcomp_resistor = {200, 81, 162},
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/* Palkia Rcomp target values */
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.rcomp_targets = {100, 40, 40, 23, 40},
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/* Set CaVref config to 0 for LPDDR3 */
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.vref_ca_config = 0,
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/* Disable Early Command Training */
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.ect = 0,
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};
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void
variant_memory_params
(
struct
cnl_mb_cfg
*bcfg)
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{
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memcpy
(bcfg, &
baseboard_memcfg
,
sizeof
(
baseboard_memcfg
));
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}
memcpy
void * memcpy(void *dest, const void *src, size_t n)
Definition:
memcpy.c:7
cnl_memcfg_init.h
DDR_CH0
@ DDR_CH0
Definition:
cnl_memcfg_init.h:23
DDR_CH1
@ DDR_CH1
Definition:
cnl_memcfg_init.h:24
variant_memory_params
const struct mb_cfg *__weak variant_memory_params(void)
Definition:
memory.c:67
baseboard_memcfg
static const struct cnl_mb_cfg baseboard_memcfg
Definition:
memory.c:10
string.h
cnl_mb_cfg
Definition:
cnl_memcfg_init.h:55
cnl_mb_cfg::dqs_map
uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS]
Definition:
cnl_memcfg_init.h:83
src
mainboard
google
hatch
variants
palkia
memory.c
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