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Macros
cortex_a57.h File Reference

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Macros

#define CPUACTLR_EL1   s3_1_c15_c2_0
 
#define BTB_INVALIDATE   (1 << 0)
 
#define CPUECTLR_EL1   S3_1_c15_c2_1
 
#define SMPEN_SHIFT   6
 
#define CORTEX_A53_PN   0xd03
 
#define OSDLR_DBL_LOCK_BIT   1
 

Macro Definition Documentation

◆ BTB_INVALIDATE

#define BTB_INVALIDATE   (1 << 0)

Definition at line 7 of file cortex_a57.h.

◆ CORTEX_A53_PN

#define CORTEX_A53_PN   0xd03

Definition at line 13 of file cortex_a57.h.

◆ CPUACTLR_EL1

#define CPUACTLR_EL1   s3_1_c15_c2_0

Definition at line 6 of file cortex_a57.h.

◆ CPUECTLR_EL1

#define CPUECTLR_EL1   S3_1_c15_c2_1

Definition at line 9 of file cortex_a57.h.

◆ OSDLR_DBL_LOCK_BIT

#define OSDLR_DBL_LOCK_BIT   1

Definition at line 16 of file cortex_a57.h.

◆ SMPEN_SHIFT

#define SMPEN_SHIFT   6

Definition at line 10 of file cortex_a57.h.