7 #include <PlatformMemoryConfiguration.h>
54 static const PCIe_PORT_DESCRIPTOR
PortList[] = {
58 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
59 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
68 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
69 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
78 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
79 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
88 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
89 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
97 DESCRIPTOR_TERMINATE_LIST,
98 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
99 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
107 static const PCIe_DDI_DESCRIPTOR
DdiList[] = {
111 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
112 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
117 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
118 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
123 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
124 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
129 .Flags = DESCRIPTOR_TERMINATE_LIST,
137 FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
138 FchReset->Xhci0Enable =
CONFIG(HUDSON_XHCI_ENABLE);
139 FchReset->Xhci1Enable =
CONFIG(HUDSON_XHCI_ENABLE);
144 InitEarly->GnbConfig.PcieComplexList = &
PcieComplex;
160 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
161 NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
180 InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex
static const PCIe_DDI_DESCRIPTOR DdiList[]
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[]
static const PCIe_PORT_DESCRIPTOR PortList[]