#include <arch/io.h>
#include <pc80/isa-dma.h>
Go to the source code of this file.
◆ DMA1_CLEAR_FF_REG
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
◆ DMA1_CLR_MASK_REG
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ |
◆ DMA1_CMD_REG
#define DMA1_CMD_REG 0x08 /* command register (w) */ |
◆ DMA1_MASK_ALL_REG
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ |
◆ DMA1_MASK_REG
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ |
◆ DMA1_MODE_REG
#define DMA1_MODE_REG 0x0B /* mode register (w) */ |
◆ DMA1_REQ_REG
#define DMA1_REQ_REG 0x09 /* request register (w) */ |
◆ DMA1_RESET_REG
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
◆ DMA1_STAT_REG
#define DMA1_STAT_REG 0x08 /* status register (r) */ |
◆ DMA1_TEMP_REG
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ |
◆ DMA2_CLEAR_FF_REG
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
◆ DMA2_CLR_MASK_REG
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ |
◆ DMA2_CMD_REG
#define DMA2_CMD_REG 0xD0 /* command register (w) */ |
◆ DMA2_MASK_ALL_REG
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ |
◆ DMA2_MASK_REG
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
◆ DMA2_MODE_REG
#define DMA2_MODE_REG 0xD6 /* mode register (w) */ |
◆ DMA2_REQ_REG
#define DMA2_REQ_REG 0xD2 /* request register (w) */ |
◆ DMA2_RESET_REG
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
◆ DMA2_STAT_REG
#define DMA2_STAT_REG 0xD0 /* status register (r) */ |
◆ DMA2_TEMP_REG
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ |
◆ DMA_AUTOINIT
#define DMA_AUTOINIT 0x10 |
◆ DMA_MODE_CASCADE
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
◆ DMA_MODE_READ
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
◆ DMA_MODE_WRITE
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
◆ isa_dma_init()