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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <raminit_common.h>
Data Fields | |
union { | |
struct { | |
u32 command: 16 | |
u32 ranksel_ap: 2 | |
u32 __pad0__: 14 | |
} | |
u32 raw | |
} | sp_cmd_ctrl |
union { | |
struct { | |
u32 cmd_executions: 9 | |
u32 __pad0__: 1 | |
u32 cmd_delay_gap: 5 | |
u32 __pad1__: 1 | |
u32 post_ssq_wait: 9 | |
u32 __pad2__: 1 | |
u32 data_direction: 2 | |
u32 __pad3__: 4 | |
} | |
u32 raw | |
} | subseq_ctrl |
union { | |
struct { | |
u32 address: 16 | |
u32 rowbits: 3 | |
u32 __pad0__: 1 | |
u32 bank: 3 | |
u32 __pad1__: 1 | |
u32 rank: 2 | |
u32 __pad2__: 6 | |
} | |
u32 raw | |
} | sp_cmd_addr |
union { | |
struct { | |
u32 inc_addr_1: 1 | |
u32 inc_addr_8: 1 | |
u32 inc_bank: 1 | |
u32 inc_rank: 2 | |
u32 addr_wrap: 5 | |
u32 lfsr_upd: 2 | |
u32 upd_rate: 4 | |
u32 lfsr_xors: 2 | |
u32 __pad0__: 14 | |
} | |
u32 raw | |
} | addr_update |
Definition at line 32 of file raminit_common.h.
u32 iosav_ssq::__pad0__ |
Definition at line 38 of file raminit_common.h.
u32 iosav_ssq::__pad1__ |
Definition at line 49 of file raminit_common.h.
u32 iosav_ssq::__pad2__ |
Definition at line 51 of file raminit_common.h.
u32 iosav_ssq::__pad3__ |
Definition at line 53 of file raminit_common.h.
union { ... } iosav_ssq::addr_update |
u32 iosav_ssq::addr_wrap |
Definition at line 79 of file raminit_common.h.
u32 iosav_ssq::address |
Definition at line 61 of file raminit_common.h.
u32 iosav_ssq::bank |
Definition at line 64 of file raminit_common.h.
Referenced by channel_scrub(), and iosav_write_jedec_write_leveling_sequence().
u32 iosav_ssq::cmd_delay_gap |
Definition at line 48 of file raminit_common.h.
u32 iosav_ssq::cmd_executions |
Definition at line 46 of file raminit_common.h.
u32 iosav_ssq::command |
Definition at line 36 of file raminit_common.h.
Referenced by channel_scrub(), dram_mrscommands(), get_power_down_mode(), iosav_write_aggressive_write_read_sequence(), iosav_write_command_training_sequence(), iosav_write_data_write_sequence(), iosav_write_jedec_write_leveling_sequence(), iosav_write_memory_test_sequence(), iosav_write_misc_write_sequence(), iosav_write_prea_act_read_sequence(), iosav_write_prea_sequence(), iosav_write_read_mpr_sequence(), iosav_write_zqcs_sequence(), and train_write_flyby().
u32 iosav_ssq::data_direction |
Definition at line 52 of file raminit_common.h.
u32 iosav_ssq::inc_addr_1 |
Definition at line 75 of file raminit_common.h.
u32 iosav_ssq::inc_addr_8 |
Definition at line 76 of file raminit_common.h.
u32 iosav_ssq::inc_bank |
Definition at line 77 of file raminit_common.h.
u32 iosav_ssq::inc_rank |
Definition at line 78 of file raminit_common.h.
u32 iosav_ssq::lfsr_upd |
Definition at line 80 of file raminit_common.h.
u32 iosav_ssq::lfsr_xors |
Definition at line 82 of file raminit_common.h.
u32 iosav_ssq::post_ssq_wait |
Definition at line 50 of file raminit_common.h.
u32 iosav_ssq::rank |
Definition at line 66 of file raminit_common.h.
Referenced by dram_mr0(), dram_mr1(), dram_mr2(), and dram_mr3().
u32 iosav_ssq::ranksel_ap |
Definition at line 37 of file raminit_common.h.
u32 iosav_ssq::raw |
Definition at line 40 of file raminit_common.h.
Referenced by iosav_write_sequence().
u32 iosav_ssq::rowbits |
Definition at line 62 of file raminit_common.h.
union { ... } iosav_ssq::sp_cmd_addr |
union { ... } iosav_ssq::sp_cmd_ctrl |
Referenced by channel_scrub(), dram_mrscommands(), get_power_down_mode(), iosav_write_aggressive_write_read_sequence(), iosav_write_command_training_sequence(), iosav_write_data_write_sequence(), iosav_write_jedec_write_leveling_sequence(), iosav_write_memory_test_sequence(), iosav_write_misc_write_sequence(), iosav_write_prea_act_read_sequence(), iosav_write_prea_sequence(), iosav_write_read_mpr_sequence(), iosav_write_zqcs_sequence(), and train_write_flyby().
union { ... } iosav_ssq::subseq_ctrl |
u32 iosav_ssq::upd_rate |
Definition at line 81 of file raminit_common.h.