3 #ifndef RAMINIT_COMMON_H
4 #define RAMINIT_COMMON_H
11 #define NUM_CHANNELS 2
12 #define NUM_SLOTRANKS 4
17 #define IOSAV_MRS (0xf000)
18 #define IOSAV_PRE (0xf002)
19 #define IOSAV_ZQCS (0xf003)
20 #define IOSAV_ACT (0xf006)
21 #define IOSAV_RD (0xf105)
22 #define IOSAV_NOP_ALT (0xf107)
23 #define IOSAV_WR (0xf201)
24 #define IOSAV_NOP (0xf207)
302 #define NUM_PATTERNS 4
307 #define MRC_CACHE_VERSION 5
422 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
424 #define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++)
425 #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
426 #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))
427 #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel])
428 #define MAX_EDGE_TIMING 71
429 #define MAX_TX_DQ 127
430 #define MAX_TX_DQS 511
431 #define MAX_RCVEN 127
442 #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1)
443 #define GET_ERR_CHANNEL(x) (x >> 16)
static struct dramc_channel const ch[2]
int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap)
void normalize_training(ramctr_timing *ctrl)
void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer)
void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank)
int command_training(ramctr_timing *ctrl)
void iosav_write_command_training_sequence(ramctr_timing *ctrl, int channel, int slotrank, unsigned int address)
bool get_host_ecc_cap(void)
int aggressive_write_training(ramctr_timing *ctrl)
int aggressive_read_training(ramctr_timing *ctrl)
void dram_dimm_set_mapping(ramctr_timing *ctrl, int training)
void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank)
struct dimm_info_st dimm_info
void set_read_write_timings(ramctr_timing *ctrl)
void dram_mrscommands(ramctr_timing *ctrl)
struct ramctr_timing_st ramctr_timing
void iosav_write_read_mpr_sequence(int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2)
void set_normal_operation(ramctr_timing *ctrl)
void restore_timings(ramctr_timing *ctrl)
void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap)
void dram_find_common_params(ramctr_timing *ctrl)
void program_timings(ramctr_timing *ctrl, int channel)
void prepare_training(ramctr_timing *ctrl)
void final_registers(ramctr_timing *ctrl)
void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2)
void iosav_run_once_and_wait(const int ch)
void channel_scrub(ramctr_timing *ctrl)
void dram_xover(ramctr_timing *ctrl)
void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank)
int read_mpr_training(ramctr_timing *ctrl)
void wait_for_iosav(int channel)
void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length)
bool get_host_ecc_forced(void)
void dram_dimm_mapping(ramctr_timing *ctrl)
void dram_zones(ramctr_timing *ctrl, int training)
int channel_test(ramctr_timing *ctrl)
void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank)
void dram_jedecreset(ramctr_timing *ctrl)
void set_wmm_behavior(const u32 cpu)
void iosav_write_jedec_write_leveling_sequence(ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg)
void dram_timing_regs(ramctr_timing *ctrl)
int receive_enable_calibration(ramctr_timing *ctrl)
int write_training(ramctr_timing *ctrl)
void set_scrambling_seed(ramctr_timing *ctrl)
struct dimm_attr_ddr3_st dimm[NUM_CHANNELS][NUM_SLOTS]
If this table is filled and put in CBMEM, then these info in CBMEM will be used to generate smbios ty...
union iosav_ssq::@335 subseq_ctrl
union iosav_ssq::@337 addr_update
union iosav_ssq::@334 sp_cmd_ctrl
union iosav_ssq::@336 sp_cmd_addr
struct ram_rank_timings::ram_lane_timings lanes[NUM_LANES]
int extended_temperature_range
int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]
u32 cmd_stretch[NUM_CHANNELS]
u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]
int ref_card_offset[NUM_CHANNELS]
int channel_size_mb[NUM_CHANNELS]
u32 mad_dimm[NUM_CHANNELS]