coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
port_descriptors.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/platform_descriptors.h>
4 #include <soc/soc_util.h>
5 #include <types.h>
6 
7 static const fsp_dxio_descriptor pco_dxio_descriptors[] = {
8  { /* MXM */
9  .port_present = true,
10  .engine_type = PCIE_ENGINE,
11  .start_logical_lane = 8,
12  .end_logical_lane = 15,
13  .device_number = 1,
14  .function_number = 1,
15  .link_aspm = ASPM_L1,
16  .link_aspm_L1_1 = true,
17  .link_aspm_L1_2 = true,
18  .turn_off_unused_lanes = true,
19  .clk_req = CLK_REQ6
20  },
21  { /* SSD */
22  .port_present = true,
23  .engine_type = PCIE_ENGINE,
24  .start_logical_lane = 0,
25  .end_logical_lane = 1,
26  .device_number = 1,
27  .function_number = 7,
28  .link_aspm = ASPM_L1,
29  .link_aspm_L1_1 = true,
30  .link_aspm_L1_2 = true,
31  .turn_off_unused_lanes = true,
32  .clk_req = CLK_REQ5
33  },
34  { /* WLAN */
35  .port_present = true,
36  .engine_type = PCIE_ENGINE,
37  .start_logical_lane = 4,
38  .end_logical_lane = 4,
39  .device_number = 1,
40  .function_number = 2,
41  .link_aspm = ASPM_L1,
42  .link_aspm_L1_1 = true,
43  .link_aspm_L1_2 = true,
44  .turn_off_unused_lanes = true,
45  .clk_req = CLK_REQ0
46  },
47  { /* LAN */
48  .port_present = true,
49  .engine_type = PCIE_ENGINE,
50  .start_logical_lane = 5,
51  .end_logical_lane = 5,
52  .device_number = 1,
53  .function_number = 3,
54  .link_aspm = ASPM_L1,
55  .link_aspm_L1_1 = true,
56  .link_aspm_L1_2 = true,
57  .turn_off_unused_lanes = true,
58  .clk_req = CLK_REQ1
59  },
60  { /* WWAN */
61  .port_present = true,
62  .engine_type = PCIE_ENGINE,
63  .start_logical_lane = 6,
64  .end_logical_lane = 6,
65  .device_number = 1,
66  .function_number = 4,
67  .link_aspm = ASPM_L1,
68  .link_aspm_L1_1 = true,
69  .link_aspm_L1_2 = true,
70  .turn_off_unused_lanes = true,
71  .clk_req = CLK_REQ2
72  },
73  { /* WIFI */
74  .port_present = true,
75  .engine_type = PCIE_ENGINE,
76  .start_logical_lane = 7,
77  .end_logical_lane = 7,
78  .gpio_group_id = 1,
79  .device_number = 1,
80  .function_number = 5,
81  .link_aspm = ASPM_L1,
82  .link_aspm_L1_1 = true,
83  .link_aspm_L1_2 = true,
84  .turn_off_unused_lanes = true,
85  .clk_req = CLK_REQ3
86  },
87  { /* SATA EXPRESS */
88  .port_present = true,
89  .engine_type = SATA_ENGINE,
90  .start_logical_lane = 2,
91  .end_logical_lane = 3,
92  .gpio_group_id = 1,
93  .channel_type = SATA_CHANNEL_LONG,
94  }
95 };
96 
97 static const fsp_dxio_descriptor dali_dxio_descriptors[] = {
98  { /* MXM */
99  .port_present = true,
100  .engine_type = PCIE_ENGINE,
101  .start_logical_lane = 8,
102  .end_logical_lane = 11,
103  .device_number = 1,
104  .function_number = 1,
105  .link_aspm = ASPM_L1,
106  .link_aspm_L1_1 = true,
107  .link_aspm_L1_2 = true,
108  .turn_off_unused_lanes = true,
109  .clk_req = CLK_REQ6
110  },
111  { /* SSD */
112  .port_present = true,
113  .engine_type = PCIE_ENGINE,
114  .start_logical_lane = 0,
115  .end_logical_lane = 1,
116  .device_number = 1,
117  .function_number = 7,
118  .link_aspm = ASPM_L1,
119  .link_aspm_L1_1 = true,
120  .link_aspm_L1_2 = true,
121  .turn_off_unused_lanes = true,
122  .clk_req = CLK_REQ5
123  },
124  { /* WLAN */
125  .port_present = true,
126  .engine_type = PCIE_ENGINE,
127  .start_logical_lane = 4,
128  .end_logical_lane = 4,
129  .device_number = 1,
130  .function_number = 2,
131  .link_aspm = ASPM_L1,
132  .link_aspm_L1_1 = true,
133  .link_aspm_L1_2 = true,
134  .turn_off_unused_lanes = true,
135  .clk_req = CLK_REQ0
136  },
137  { /* LAN */
138  .port_present = true,
139  .engine_type = PCIE_ENGINE,
140  .start_logical_lane = 5,
141  .end_logical_lane = 5,
142  .device_number = 1,
143  .function_number = 3,
144  .link_aspm = ASPM_L1,
145  .link_aspm_L1_1 = true,
146  .link_aspm_L1_2 = true,
147  .turn_off_unused_lanes = true,
148  .clk_req = CLK_REQ1
149  },
150  { /* SATA */
151  .port_present = true,
152  .engine_type = SATA_ENGINE,
153  .start_logical_lane = 2,
154  .end_logical_lane = 3,
155  .gpio_group_id = 1,
156  .channel_type = SATA_CHANNEL_LONG,
157  }
158 };
159 
160 static const fsp_ddi_descriptor pco_ddi_descriptors[] = {
161  { /* DDI0 - DP */
162  .connector_type = DP,
163  .aux_index = AUX1,
164  .hdp_index = HDP1
165  },
166  { /* DDI1 - eDP */
167  .connector_type = EDP,
168  .aux_index = AUX2,
169  .hdp_index = HDP2
170  },
171  { /* DDI2 - DP */
172  .connector_type = DP,
173  .aux_index = AUX3,
174  .hdp_index = HDP3,
175  },
176  { /* DDI3 - DP */
177  .connector_type = DP,
178  .aux_index = AUX4,
179  .hdp_index = HDP4,
180  }
181 };
182 
183 static const fsp_ddi_descriptor dali_ddi_descriptors[] = {
184  { /* DDI0 - DP */
185  .connector_type = DP,
186  .aux_index = AUX1,
187  .hdp_index = HDP1
188  },
189  { /* DDI1 - eDP */
190  .connector_type = EDP,
191  .aux_index = AUX2,
192  .hdp_index = HDP2
193  },
194  { /* DDI2 - DP */
195  .connector_type = DP,
196  .aux_index = AUX4,
197  .hdp_index = HDP4,
198  }
199 };
200 
201 void mainboard_get_dxio_ddi_descriptors(
202  const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
203  const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
204 {
205  if (soc_is_reduced_io_sku()) { /* Dali */
206  *dxio_descs = dali_dxio_descriptors;
207  *dxio_num = ARRAY_SIZE(dali_dxio_descriptors);
208  *ddi_descs = dali_ddi_descriptors;
209  *ddi_num = ARRAY_SIZE(dali_ddi_descriptors);
210  } else { /* Picasso and default */
211  *dxio_descs = pco_dxio_descriptors;
212  *dxio_num = ARRAY_SIZE(pco_dxio_descriptors);
213  *ddi_descs = pco_ddi_descriptors;
214  *ddi_num = ARRAY_SIZE(pco_ddi_descriptors);
215  }
216 }
mainboard_get_dxio_ddi_descriptors
void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
Definition: port_descriptors.c:77
dali_ddi_descriptors
static const fsp_ddi_descriptor dali_ddi_descriptors[]
Definition: port_descriptors.c:183
dali_dxio_descriptors
static const fsp_dxio_descriptor dali_dxio_descriptors[]
Definition: port_descriptors.c:97
pco_ddi_descriptors
static const fsp_ddi_descriptor pco_ddi_descriptors[]
Definition: port_descriptors.c:160
pco_dxio_descriptors
static const fsp_dxio_descriptor pco_dxio_descriptors[]
Definition: port_descriptors.c:7
soc_is_reduced_io_sku
bool soc_is_reduced_io_sku(void)
Definition: soc_util.c:210
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: helpers.h:12
ASPM_L1
@ ASPM_L1
Definition: pcie_rp.h:50