coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
addressmap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
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#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
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enum
{
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MCUSYS_BASE
= 0x0C530000,
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IO_PHYS
= 0x10000000,
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};
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enum
{
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MCUCFG_BASE
=
MCUSYS_BASE
+ 0x00008000,
13
};
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enum
{
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CKSYS_BASE
=
IO_PHYS
+ 0x00000000,
17
INFRACFG_AO_BASE
=
IO_PHYS
+ 0x00001000,
18
IOCFG_LT_BASE
=
IO_PHYS
+ 0x00002000,
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IOCFG_LM_BASE
=
IO_PHYS
+ 0x00002200,
20
IOCFG_LB_BASE
=
IO_PHYS
+ 0x00002400,
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IOCFG_BL_BASE
=
IO_PHYS
+ 0x00002600,
22
IOCFG_RB_BASE
=
IO_PHYS
+ 0x00002A00,
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IOCFG_RT_BASE
=
IO_PHYS
+ 0x00002C00,
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PERICFG_BASE
=
IO_PHYS
+ 0x00003000,
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GPIO_BASE
=
IO_PHYS
+ 0x00005000,
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SPM_BASE
=
IO_PHYS
+ 0x00006000,
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RGU_BASE
=
IO_PHYS
+ 0x00007000,
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GPT_BASE
=
IO_PHYS
+ 0x00008000,
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EINT_BASE
=
IO_PHYS
+ 0x0000B000,
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APMIXED_BASE
=
IO_PHYS
+ 0x0000C000,
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PWRAP_BASE
=
IO_PHYS
+ 0x0000D000,
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DEVAPC_AO_INFRA_PERI_BASE
=
IO_PHYS
+ 0x0000E000,
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DEVAPC_AO_MM_BASE
=
IO_PHYS
+ 0x0000F000,
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PMIF_BASE
=
IO_PHYS
+ 0x00015000,
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SYSTIMER_BASE
=
IO_PHYS
+ 0x00017000,
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I2C0_DMA_BASE
=
IO_PHYS
+ 0x00200100,
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I2C1_DMA_BASE
=
IO_PHYS
+ 0x00200200,
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I2C2_DMA_BASE
=
IO_PHYS
+ 0x00200300,
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I2C3_DMA_BASE
=
IO_PHYS
+ 0x00200480,
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I2C4_DMA_BASE
=
IO_PHYS
+ 0x00200580,
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I2C5_DMA_BASE
=
IO_PHYS
+ 0x00200700,
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I2C6_DMA_BASE
=
IO_PHYS
+ 0x00200800,
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I2C7_DMA_BASE
=
IO_PHYS
+ 0x00200900,
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I2C8_DMA_BASE
=
IO_PHYS
+ 0x00200A80,
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I2C9_DMA_BASE
=
IO_PHYS
+ 0x00200C00,
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DEVAPC_BASE
=
IO_PHYS
+ 0x00207000,
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DBG_TRACKER_BASE
=
IO_PHYS
+ 0x00208000,
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EMI0_BASE
=
IO_PHYS
+ 0x00219000,
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EMI0_MPU_BASE
=
IO_PHYS
+ 0x0021B000,
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DRAMC_CHA_AO_BASE
=
IO_PHYS
+ 0x00220000,
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SSPM_SRAM_BASE
=
IO_PHYS
+ 0x00400000,
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SSPM_CFG_BASE
=
IO_PHYS
+ 0x00440000,
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SFLASH_REG_BASE
=
IO_PHYS
+ 0x01000000,
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AUXADC_BASE
=
IO_PHYS
+ 0x01001000,
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UART0_BASE
=
IO_PHYS
+ 0x01002000,
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I2C7_BASE
=
IO_PHYS
+ 0x01004000,
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I2C8_BASE
=
IO_PHYS
+ 0x01005000,
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I2C0_BASE
=
IO_PHYS
+ 0x01007000,
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I2C1_BASE
=
IO_PHYS
+ 0x01008000,
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I2C2_BASE
=
IO_PHYS
+ 0x01009000,
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SPI0_BASE
=
IO_PHYS
+ 0x0100A000,
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I2C6_BASE
=
IO_PHYS
+ 0x0100D000,
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I2C3_BASE
=
IO_PHYS
+ 0x0100F000,
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SPI1_BASE
=
IO_PHYS
+ 0x01010000,
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I2C4_BASE
=
IO_PHYS
+ 0x01011000,
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SPI2_BASE
=
IO_PHYS
+ 0x01012000,
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SPI3_BASE
=
IO_PHYS
+ 0x01013000,
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SPI4_BASE
=
IO_PHYS
+ 0x01014000,
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SPI5_BASE
=
IO_PHYS
+ 0x01015000,
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I2C5_BASE
=
IO_PHYS
+ 0x01016000,
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I2C9_BASE
=
IO_PHYS
+ 0x01019000,
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/* Corsola uses USB2 port1 instead of USB2 port0. */
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SSUSB_IPPC_BASE
=
IO_PHYS
+ 0x01283E00,
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MSDC0_BASE
=
IO_PHYS
+ 0x01230000,
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/* Corsola uses USB2 port1 instead of USB2 port0. */
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SSUSB_SIF_BASE
=
IO_PHYS
+ 0x01C80300,
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EFUSEC_BASE
=
IO_PHYS
+ 0x01CB0000,
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MIPITX_BASE
=
IO_PHYS
+ 0x01CC0000,
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MSDC0_TOP_BASE
=
IO_PHYS
+ 0x01CD0000,
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MMSYS_BASE
=
IO_PHYS
+ 0x04000000,
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DISP_MUTEX_BASE
=
IO_PHYS
+ 0x04001000,
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SMI_BASE
=
IO_PHYS
+ 0x04002000,
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SMI_LARB0
=
IO_PHYS
+ 0x04003000,
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DISP_OVL0_BASE
=
IO_PHYS
+ 0x04005000,
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DISP_OVL1_BASE
=
IO_PHYS
+ 0x04006000,
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DISP_RDMA0_BASE
=
IO_PHYS
+ 0x04007000,
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DISP_COLOR0_BASE
=
IO_PHYS
+ 0x04009000,
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DISP_CCORR0_BASE
=
IO_PHYS
+ 0x0400B000,
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DISP_AAL0_BASE
=
IO_PHYS
+ 0x0400C000,
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DISP_GAMMA0_BASE
=
IO_PHYS
+ 0x0400D000,
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DISP_POSTMASK0_BASE
=
IO_PHYS
+ 0x0400E000,
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DISP_DITHER0_BASE
=
IO_PHYS
+ 0x0400F000,
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DSI0_BASE
=
IO_PHYS
+ 0x04013000,
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};
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#endif
RGU_BASE
@ RGU_BASE
Definition:
addressmap.h:20
MMSYS_BASE
@ MMSYS_BASE
Definition:
addressmap.h:44
INFRACFG_AO_BASE
@ INFRACFG_AO_BASE
Definition:
addressmap.h:15
SPM_BASE
@ SPM_BASE
Definition:
addressmap.h:19
DSI0_BASE
@ DSI0_BASE
Definition:
addressmap.h:54
APMIXED_BASE
@ APMIXED_BASE
Definition:
addressmap.h:30
UART0_BASE
@ UART0_BASE
Definition:
addressmap.h:36
EINT_BASE
@ EINT_BASE
Definition:
addressmap.h:22
MCUCFG_BASE
@ MCUCFG_BASE
Definition:
addressmap.h:27
DISP_COLOR0_BASE
@ DISP_COLOR0_BASE
Definition:
addressmap.h:50
DISP_OVL1_BASE
@ DISP_OVL1_BASE
Definition:
addressmap.h:46
DISP_RDMA0_BASE
@ DISP_RDMA0_BASE
Definition:
addressmap.h:47
GPIO_BASE
@ GPIO_BASE
Definition:
addressmap.h:18
CKSYS_BASE
@ CKSYS_BASE
Definition:
addressmap.h:14
DISP_MUTEX_BASE
@ DISP_MUTEX_BASE
Definition:
addressmap.h:56
GPT_BASE
@ GPT_BASE
Definition:
addressmap.h:21
SFLASH_REG_BASE
@ SFLASH_REG_BASE
Definition:
addressmap.h:40
SSUSB_IPPC_BASE
@ SSUSB_IPPC_BASE
Definition:
addressmap.h:42
SSUSB_SIF_BASE
@ SSUSB_SIF_BASE
Definition:
addressmap.h:43
DISP_OVL0_BASE
@ DISP_OVL0_BASE
Definition:
addressmap.h:45
IO_PHYS
@ IO_PHYS
Definition:
addressmap.h:10
IOCFG_LT_BASE
@ IOCFG_LT_BASE
Definition:
addressmap.h:46
DISP_AAL0_BASE
@ DISP_AAL0_BASE
Definition:
addressmap.h:57
SPI2_BASE
@ SPI2_BASE
Definition:
addressmap.h:32
IOCFG_LM_BASE
@ IOCFG_LM_BASE
Definition:
addressmap.h:43
PWRAP_BASE
@ PWRAP_BASE
Definition:
addressmap.h:20
AUXADC_BASE
@ AUXADC_BASE
Definition:
addressmap.h:27
EFUSEC_BASE
@ EFUSEC_BASE
Definition:
addressmap.h:45
SSPM_SRAM_BASE
@ SSPM_SRAM_BASE
Definition:
addressmap.h:24
DISP_GAMMA0_BASE
@ DISP_GAMMA0_BASE
Definition:
addressmap.h:58
SSPM_CFG_BASE
@ SSPM_CFG_BASE
Definition:
addressmap.h:25
MIPITX_BASE
@ MIPITX_BASE
Definition:
addressmap.h:41
SMI_BASE
@ SMI_BASE
Definition:
addressmap.h:63
SPI3_BASE
@ SPI3_BASE
Definition:
addressmap.h:33
IOCFG_RB_BASE
@ IOCFG_RB_BASE
Definition:
addressmap.h:40
SPI4_BASE
@ SPI4_BASE
Definition:
addressmap.h:34
IOCFG_BL_BASE
@ IOCFG_BL_BASE
Definition:
addressmap.h:44
DISP_CCORR0_BASE
@ DISP_CCORR0_BASE
Definition:
addressmap.h:56
SPI1_BASE
@ SPI1_BASE
Definition:
addressmap.h:31
SPI5_BASE
@ SPI5_BASE
Definition:
addressmap.h:35
DISP_DITHER0_BASE
@ DISP_DITHER0_BASE
Definition:
addressmap.h:59
IOCFG_RT_BASE
@ IOCFG_RT_BASE
Definition:
addressmap.h:38
SMI_LARB0
@ SMI_LARB0
Definition:
addressmap.h:62
SPI0_BASE
@ SPI0_BASE
Definition:
addressmap.h:30
IOCFG_LB_BASE
@ IOCFG_LB_BASE
Definition:
addressmap.h:42
I2C6_BASE
@ I2C6_BASE
Definition:
addressmap.h:62
I2C7_DMA_BASE
@ I2C7_DMA_BASE
Definition:
addressmap.h:43
I2C3_BASE
@ I2C3_BASE
Definition:
addressmap.h:63
DRAMC_CHA_AO_BASE
@ DRAMC_CHA_AO_BASE
Definition:
addressmap.h:50
DEVAPC_AO_MM_BASE
@ DEVAPC_AO_MM_BASE
Definition:
addressmap.h:33
DISP_POSTMASK0_BASE
@ DISP_POSTMASK0_BASE
Definition:
addressmap.h:91
DEVAPC_BASE
@ DEVAPC_BASE
Definition:
addressmap.h:46
I2C3_DMA_BASE
@ I2C3_DMA_BASE
Definition:
addressmap.h:39
PMIF_BASE
@ PMIF_BASE
Definition:
addressmap.h:34
I2C0_DMA_BASE
@ I2C0_DMA_BASE
Definition:
addressmap.h:36
DBG_TRACKER_BASE
@ DBG_TRACKER_BASE
Definition:
addressmap.h:47
DEVAPC_AO_INFRA_PERI_BASE
@ DEVAPC_AO_INFRA_PERI_BASE
Definition:
addressmap.h:32
I2C4_BASE
@ I2C4_BASE
Definition:
addressmap.h:65
I2C8_BASE
@ I2C8_BASE
Definition:
addressmap.h:57
PERICFG_BASE
@ PERICFG_BASE
Definition:
addressmap.h:24
I2C2_DMA_BASE
@ I2C2_DMA_BASE
Definition:
addressmap.h:38
SYSTIMER_BASE
@ SYSTIMER_BASE
Definition:
addressmap.h:35
I2C5_BASE
@ I2C5_BASE
Definition:
addressmap.h:70
I2C5_DMA_BASE
@ I2C5_DMA_BASE
Definition:
addressmap.h:41
I2C8_DMA_BASE
@ I2C8_DMA_BASE
Definition:
addressmap.h:44
EMI0_MPU_BASE
@ EMI0_MPU_BASE
Definition:
addressmap.h:49
I2C1_BASE
@ I2C1_BASE
Definition:
addressmap.h:59
EMI0_BASE
@ EMI0_BASE
Definition:
addressmap.h:48
I2C1_DMA_BASE
@ I2C1_DMA_BASE
Definition:
addressmap.h:37
MSDC0_BASE
@ MSDC0_BASE
Definition:
addressmap.h:74
I2C9_DMA_BASE
@ I2C9_DMA_BASE
Definition:
addressmap.h:45
I2C0_BASE
@ I2C0_BASE
Definition:
addressmap.h:58
I2C7_BASE
@ I2C7_BASE
Definition:
addressmap.h:56
I2C2_BASE
@ I2C2_BASE
Definition:
addressmap.h:60
I2C9_BASE
@ I2C9_BASE
Definition:
addressmap.h:71
MSDC0_TOP_BASE
@ MSDC0_TOP_BASE
Definition:
addressmap.h:79
I2C6_DMA_BASE
@ I2C6_DMA_BASE
Definition:
addressmap.h:42
I2C4_DMA_BASE
@ I2C4_DMA_BASE
Definition:
addressmap.h:40
MCUSYS_BASE
@ MCUSYS_BASE
Definition:
addressmap.h:7
src
soc
mediatek
mt8186
include
soc
addressmap.h
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