3 #ifndef SOC_MEDIATEK_MT8183_SPM_H
4 #define SOC_MEDIATEK_MT8183_SPM_H
6 #include <soc/addressmap.h>
11 #define SPM_PROJECT_CODE 0xb16
12 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
15 #define BCLK_CG_EN_LSB (1U << 0)
16 #define MD_BCLK_CG_EN_LSB (1U << 1)
17 #define PCM_IM_HOST_W_EN_LSB (1U << 30)
18 #define PCM_IM_HOST_EN_LSB (1U << 31)
21 #define SYSCLK0_EN_CTRL_LSB (1U << 0)
22 #define SYSCLK1_EN_CTRL_LSB (1U << 2)
23 #define SPM_LOCK_INFRA_DCM_LSB (1U << 5)
24 #define EXT_SRCCLKEN_MASK (1U << 6)
25 #define CXO32K_REMOVE_EN_MD1_LSB (1U << 9)
26 #define CLKSQ1_SEL_CTRL_LSB (1U << 12)
27 #define SRCLKEN0_EN_LSB (1U << 13)
30 #define PCM_KICK_L_LSB (1U << 0)
31 #define IM_KICK_L_LSB (1U << 1)
32 #define PCM_CK_EN_LSB (1U << 2)
33 #define EN_IM_SLEEP_DVS_LSB (1U << 3)
34 #define IM_AUTO_PDN_EN_LSB (1U << 4)
35 #define PCM_SW_RESET_LSB (1U << 15)
38 #define IM_SLAVE_LSB (1U << 0)
39 #define IM_SLEEP_LSB (1U << 1)
40 #define MIF_APBEN_LSB (1U << 3)
41 #define IM_PDN_LSB (1U << 4)
42 #define PCM_TIMER_EN_LSB (1U << 5)
43 #define IM_NONRP_EN_LSB (1U << 6)
44 #define DIS_MIF_PROT_LSB (1U << 7)
45 #define PCM_WDT_EN_LSB (1U << 8)
46 #define PCM_WDT_WAKE_MODE_LSB (1U << 9)
47 #define SPM_SRAM_SLEEP_B_LSB (1U << 10)
48 #define SPM_SRAM_ISOINT_B_LSB (1U << 11)
49 #define EVENT_LOCK_EN_LSB (1U << 12)
50 #define SRCCLKEN_FAST_RESP_LSB (1U << 13)
51 #define SCP_APB_INTERNAL_EN_LSB (1U << 14)
54 #define PCM_IRQ_ROOT_MASK_LSB (1U << 3)
57 #define WAKEUP_EVENT_MASK_B_BIT0 (1U << 0)
60 #define SPARE1_DDREN_MASK_B_LSB (1U << 0)
63 #define SPM_PC_TRACE_OFFSET_LSB (1U << 0)
64 #define SPM_PC_TRACE_OFFSET (1U << 3)
65 #define SPM_PC_TRACE_HW_EN_LSB (1U << 16)
68 #define SPARE_ACK_MASK_B_BIT0 (1U << 0)
69 #define SPARE_ACK_MASK_B_BIT1 (1U << 1)
74 #define CONN_DDR_EN_DBC_LEN (0x00000154 << 20)
75 #define IFR_SRAMROM_ROM_PDN (0x0000003f)
76 #define IM_STATE (0x4 << 7)
77 #define IM_STATE_MASK (0x7 << 7)
78 #define MD_DDR_EN_0_DBC_LEN (0x00000154)
79 #define MD_DDR_EN_1_DBC_LEN (0x00000154 << 10)
80 #define PCM_FSM_STA_DEF (0x00108490)
81 #define PCM_FSM_STA_MASK (0x7FFFFF)
82 #define POWER_ON_VAL1_DEF (0x00015800)
83 #define SPM_CORE_TIMEOUT (5000)
84 #define SPM_MAS_PAUSE_MASK_B_VAL (0xFFFFFFFF)
85 #define SPM_MAS_PAUSE2_MASK_B_VAL (0xFFFFFFFF)
86 #define SPM_PCM_REG1_DATA_CHECK (0x1)
87 #define SPM_PCM_REG15_DATA_CHECK (0x0)
88 #define SPM_WAKEUP_EVENT_MASK_DEF (0xF0F92218)
89 #define SYSCLK1_EN_CTRL (0x3 << 2)
90 #define SYSCLK1_SRC_MASK_B (0x10 << 23)
96 #define ISRM_TWAM (1U << 2)
97 #define ISRM_PCM_RETURN (1U << 3)
98 #define ISRM_RET_IRQ_AUX (0x3FF00)
99 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
100 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
103 #define ISRS_TWAM (1U << 2)
104 #define ISRS_PCM_RETURN (1U << 3)
105 #define ISRS_SW_INT0 (1U << 4)
106 #define ISRC_TWAM (ISRS_TWAM)
107 #define ISRC_ALL_EXC_TWAM (ISRS_PCM_RETURN)
108 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
111 #define PCM_PWRIO_EN_R0 (1U << 0)
112 #define PCM_PWRIO_EN_R7 (1U << 7)
113 #define PCM_RF_SYNC_R0 (1U << 16)
114 #define PCM_RF_SYNC_R6 (1U << 22)
115 #define PCM_RF_SYNC_R7 (1U << 23)
118 #define PCM_SW_INT_ALL (0x3FF)
129 #define PCM_EVENT_VECTOR_NUM 16
check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c)
static const struct power_domain_data disp[]
#define PCM_EVENT_VECTOR_NUM
@ DYNA_LOAD_PCM_SUSPEND_LP4_3733
@ DYNA_LOAD_PCM_SUSPEND_LP4_3200
static struct mtk_spm_regs *const mtk_spm
static const struct power_domain_data audio[]
u32 pcm_event_vector[PCM_EVENT_VECTOR_NUM]
u32 dvfs_abort_others_mask
u32 dvfsrc_event_force_on
u32 mp0_cputop_l2_sleep_b
u32 emi_self_refresh_ch_sta
u32 dvfsrc_event_mask_con
u32 pcm_reg12_ext_mask_b_sta
u32 dramc_dpy_clk_sw_con_sel
u8 reserved19[0x720 - 0x618]
u8 reserved26[0xb00 - 0x924]
u32 spm_mas_pause_mm_mask_b
u32 spm_mas_pause_mcu_mask_b
u8 reserved30[0xf00 - 0xb70]
u32 spm_wakeup_event_ext_mask
u32 spm_mas_pause2_mask_b
u32 dramc_dpy_clk_sw_con_rsv
u32 dramc_dpy_clk_sw_con2
u32 spm_wakeup_event_mask
u32 mp1_cputop_l2_sleep_b
u32 dramc_dpy_clk_sw_con_sel2
u32 mbist_efuse_repair_ack_sta
u32 vector[PCM_EVENT_VECTOR_NUM]