coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
elog.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi_pm.h>
4 #include <bootstate.h>
5 #include <stdint.h>
6 #include <elog.h>
7 #include <soc/lpc.h>
8 #include <soc/pm.h>
9 
10 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
11 {
12  int i;
13 
14  gpe0_sts &= gpe0_en;
15 
16  for (i = 0; i <= 31; i++) {
17  if (gpe0_sts & (1 << i))
19  }
20 }
21 
22 static void pch_log_wake_source(const struct chipset_power_state *ps)
23 {
24  /* Power Button */
25  if (ps->pm1_sts & PWRBTN_STS)
27 
28  /* RTC */
29  if (ps->pm1_sts & RTC_STS)
31 
32  /* PCI Express (TODO: determine wake device) */
33  if (ps->pm1_sts & PCIEXPWAK_STS)
35 
36  /* PME (TODO: determine wake device) */
37  if (ps->gpe0_sts[GPE_STD] & PME_STS)
39 
40  /* Internal PME (TODO: determine wake device) */
41  if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
43 
44  /* SMBUS Wake */
45  if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
47 
48  /* GPIO27 */
49  if (ps->gpe0_sts[GPE_STD] & GP27_STS)
51 
52  /* Log GPIO events in set 1-3 */
56 }
57 
58 static void pch_log_power_and_resets(const struct chipset_power_state *ps)
59 {
60  /* Thermal Trip Status */
61  if (ps->gen_pmcon2 & THERMTRIP_STS)
63 
64  /* PWR_FLR Power Failure */
65  if (ps->gen_pmcon2 & PWROK_FLR)
67 
68  /* SUS Well Power Failure */
69  if (ps->gen_pmcon3 & SUS_PWR_FLR)
71 
72  /* SYS_PWROK Failure */
73  if (ps->gen_pmcon2 & SYSPWR_FLR)
75 
76  /* PWROK Failure */
77  if (ps->gen_pmcon2 & PWROK_FLR)
79 
80  /* TCO Timeout */
81  if (ps->prev_sleep_state != ACPI_S3 &&
84 
85  /* Power Button Override */
86  if (ps->pm1_sts & PRBTNOR_STS)
88 
89  /* RTC reset */
90  if (ps->gen_pmcon3 & RTC_BATTERY_DEAD)
92 
93  /* System Reset Status (reset button pushed) */
94  if (ps->gen_pmcon2 & SYSTEM_RESET_STS)
96 
97  /* General Reset Status */
98  if (ps->gen_pmcon3 & GEN_RST_STS)
100 
101  /* ACPI Wake Event */
102  if (ps->prev_sleep_state != ACPI_S0)
104 }
105 
106 static void pch_log_state(void *unused)
107 {
108  const struct chipset_power_state *ps;
109 
110  if (acpi_pm_state_for_elog(&ps) < 0)
111  return;
112 
113  /* Power and Reset */
115 
116  /* Wake Sources */
118 }
119 
int acpi_pm_state_for_elog(const struct chipset_power_state **ps)
Definition: acpi_pm.c:41
#define GPE_63_32
Definition: pm.h:83
#define GPE_31_0
Definition: pm.h:82
#define GPE_STD
Definition: pm.h:85
#define SMB_WAK_STS
Definition: pm.h:95
#define PME_STS
Definition: pm.h:92
#define PRBTNOR_STS
Definition: pm.h:15
#define PME_B0_STS
Definition: pm.h:90
#define GEN_RST_STS
Definition: pm.h:48
@ BS_DEV_INIT
Definition: bootstate.h:83
@ BS_ON_ENTRY
Definition: bootstate.h:95
#define TCO2_STS_SECOND_TO
Definition: pm.h:61
#define GP27_STS
Definition: pm.h:71
#define GPE_94_64
Definition: pm.h:68
#define PWRBTN_STS
Definition: southbridge.h:30
#define PCIEXPWAK_STS
Definition: southbridge.h:28
#define RTC_STS
Definition: southbridge.h:29
#define ELOG_WAKE_SOURCE_RTC
Definition: elog.h:154
#define ELOG_TYPE_RESET_BUTTON
Definition: elog.h:137
#define ELOG_WAKE_SOURCE_PCIE
Definition: elog.h:151
#define ELOG_TYPE_PWROK_FAIL
Definition: elog.h:130
#define ELOG_TYPE_SUS_POWER_FAIL
Definition: elog.h:129
#define ELOG_TYPE_THERM_TRIP
Definition: elog.h:277
#define ELOG_TYPE_POWER_FAIL
Definition: elog.h:128
#define ELOG_TYPE_SYS_PWROK_FAIL
Definition: elog.h:131
#define ELOG_TYPE_ACPI_WAKE
Definition: elog.h:149
#define ELOG_WAKE_SOURCE_PME
Definition: elog.h:152
#define ELOG_WAKE_SOURCE_GPE
Definition: elog.h:155
#define ELOG_WAKE_SOURCE_PWRBTN
Definition: elog.h:157
#define ELOG_WAKE_SOURCE_PME_INTERNAL
Definition: elog.h:153
#define ELOG_TYPE_POWER_BUTTON_OVERRIDE
Definition: elog.h:134
#define ELOG_TYPE_SYSTEM_RESET
Definition: elog.h:138
#define ELOG_TYPE_RTC_RESET
Definition: elog.h:139
#define ELOG_TYPE_TCO_RESET
Definition: elog.h:140
#define ELOG_WAKE_SOURCE_SMBUS
Definition: elog.h:156
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, elog_bs_init, NULL)
int elog_add_event_byte(u8 event_type, u8 data)
Definition: elog.c:868
int elog_add_event_wake(u8 source, u32 instance)
Definition: elog.c:883
int elog_add_event(u8 event_type)
Definition: elog.c:863
@ ACPI_S3
Definition: acpi.h:1383
@ ACPI_S0
Definition: acpi.h:1380
#define RTC_BATTERY_DEAD
Definition: pmc.h:61
#define SUS_PWR_FLR
Definition: pmc.h:28
void pch_log_state(void)
Definition: elog.c:88
#define PWROK_FLR
Definition: lpc.h:62
#define SYSPWR_FLR
Definition: lpc.h:61
#define THERMTRIP_STS
Definition: lpc.h:60
#define SYSTEM_RESET_STS
Definition: lpc.h:59
static void pch_log_wake_source(const struct chipset_power_state *ps)
Definition: elog.c:22
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
Definition: elog.c:10
static void pch_log_power_and_resets(const struct chipset_power_state *ps)
Definition: elog.c:58
#define NULL
Definition: stddef.h:19
uint32_t u32
Definition: stdint.h:51
uint16_t tco2_sts
Definition: pm.h:146
uint32_t gen_pmcon3
Definition: pm.h:233
uint32_t gen_pmcon2
Definition: pm.h:232
uint32_t gpe0_en[4]
Definition: pm.h:148
uint32_t prev_sleep_state
Definition: pm.h:153
uint32_t gpe0_sts[4]
Definition: pm.h:147
uint16_t pm1_sts
Definition: pm.h:142