coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smi.h
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 /*
4  * Utilities for SMI handlers and SMM setup
5  */
6 
7 #ifndef _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
8 #define _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
9 
10 #include <device/mmio.h>
11 
12 /* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
13  * This is defined by AGESA, but we dpn't include AGESA headers to avoid
14  * polluting the namesace.
15  */
16 #define SMI_BASE 0xfed80200
17 
18 #define SMI_REG_SMITRIG0 0x98
19 #define SMITRG0_EOS (1 << 28)
20 #define SMITRG0_SMIENB (1 << 31)
21 
22 #define SMI_REG_CONTROL0 0xa0
23 
24 enum smi_mode {
29 };
30 
31 enum smi_lvl {
34 };
35 
36 void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
39 
40 #endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */
smi_mode
Definition: smi.h:8
@ SMI_MODE_NMI
Definition: smi.h:11
@ SMI_MODE_IRQ13
Definition: smi.h:12
@ SMI_MODE_SMI
Definition: smi.h:10
@ SMI_MODE_DISABLE
Definition: smi.h:9
void hudson_disable_gevent_smi(uint8_t gevent)
Disable events from given GEVENT pin.
Definition: smi_util.c:63
void hudson_enable_acpi_cmd_smi(void)
Enable SMIs on writes to ACPI SMI command port.
Definition: smi_util.c:76
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
Configure generation of interrupts for given GEVENT pin.
Definition: smi_util.c:43
smi_lvl
Definition: smi.h:31
@ SMI_LVL_LOW
Definition: smi.h:32
@ SMI_LVL_HIGH
Definition: smi.h:33
unsigned char uint8_t
Definition: stdint.h:8