coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smi.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Utilities for SMI handlers and SMM setup
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*/
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#ifndef _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
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#define _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
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#include <
device/mmio.h
>
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/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
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* This is defined by AGESA, but we dpn't include AGESA headers to avoid
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* polluting the namesace.
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*/
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#define SMI_BASE 0xfed80200
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#define SMI_REG_SMITRIG0 0x98
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#define SMITRG0_EOS (1 << 28)
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#define SMITRG0_SMIENB (1 << 31)
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#define SMI_REG_CONTROL0 0xa0
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enum
smi_mode
{
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SMI_MODE_DISABLE
= 0,
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SMI_MODE_SMI
= 1,
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SMI_MODE_NMI
= 2,
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SMI_MODE_IRQ13
= 3,
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};
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enum
smi_lvl
{
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SMI_LVL_LOW
= 0,
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SMI_LVL_HIGH
= 1,
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};
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void
hudson_configure_gevent_smi
(
uint8_t
gevent,
uint8_t
mode,
uint8_t
level);
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void
hudson_disable_gevent_smi
(
uint8_t
gevent);
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void
hudson_enable_acpi_cmd_smi
(
void
);
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#endif
/* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */
mmio.h
smi_mode
smi_mode
Definition:
smi.h:8
SMI_MODE_NMI
@ SMI_MODE_NMI
Definition:
smi.h:11
SMI_MODE_IRQ13
@ SMI_MODE_IRQ13
Definition:
smi.h:12
SMI_MODE_SMI
@ SMI_MODE_SMI
Definition:
smi.h:10
SMI_MODE_DISABLE
@ SMI_MODE_DISABLE
Definition:
smi.h:9
hudson_disable_gevent_smi
void hudson_disable_gevent_smi(uint8_t gevent)
Disable events from given GEVENT pin.
Definition:
smi_util.c:63
hudson_enable_acpi_cmd_smi
void hudson_enable_acpi_cmd_smi(void)
Enable SMIs on writes to ACPI SMI command port.
Definition:
smi_util.c:76
hudson_configure_gevent_smi
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)
Configure generation of interrupts for given GEVENT pin.
Definition:
smi_util.c:43
smi_lvl
smi_lvl
Definition:
smi.h:31
SMI_LVL_LOW
@ SMI_LVL_LOW
Definition:
smi.h:32
SMI_LVL_HIGH
@ SMI_LVL_HIGH
Definition:
smi.h:33
uint8_t
unsigned char uint8_t
Definition:
stdint.h:8
src
southbridge
amd
agesa
hudson
smi.h
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