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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
Go to the source code of this file.
Macros | |
#define | SMI_BASE 0xfed80200 |
#define | SMI_REG_SMITRIG0 0x98 |
#define | SMITRG0_EOS (1 << 28) |
#define | SMITRG0_SMIENB (1 << 31) |
#define | SMI_REG_CONTROL0 0xa0 |
Enumerations | |
enum | smi_mode { SMI_MODE_DISABLE = 0 , SMI_MODE_SMI = 1 , SMI_MODE_NMI = 2 , SMI_MODE_IRQ13 = 3 , SMI_MODE_DISABLE = 0 , SMI_MODE_SMI = 1 , SMI_MODE_NMI = 2 , SMI_MODE_IRQ13 = 3 , SMI_MODE_DISABLE = 0 , SMI_MODE_SMI = 1 , SMI_MODE_NMI = 2 , SMI_MODE_IRQ13 = 3 } |
enum | smi_lvl { SMI_LVL_LOW = 0 , SMI_LVL_HIGH = 1 , SMI_LVL_LOW = 0 , SMI_LVL_HIGH = 1 } |
Functions | |
void | hudson_configure_gevent_smi (uint8_t gevent, uint8_t mode, uint8_t level) |
Configure generation of interrupts for given GEVENT pin. More... | |
void | hudson_disable_gevent_smi (uint8_t gevent) |
Disable events from given GEVENT pin. More... | |
void | hudson_enable_acpi_cmd_smi (void) |
Enable SMIs on writes to ACPI SMI command port. More... | |
enum smi_lvl |
enum smi_mode |
Configure generation of interrupts for given GEVENT pin.
gevent | The GEVENT pin number. Valid values are 0 thru 23 |
mode | The type of event this pin should generate. Note that only SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. |
level | SMI_LVL_LOW or SMI_LVL_HIGH |
Definition at line 43 of file smi_util.c.
References BIOS_WARNING, configure_smi(), printk, smi_read32(), SMI_REG_SMITRIG0, and smi_write32().
Referenced by mainboard_enable(), mainboard_smi_apmc(), and pavilion_cold_boot_init().
Disable events from given GEVENT pin.
Definition at line 63 of file smi_util.c.
References BIOS_WARNING, configure_smi(), printk, and SMI_MODE_DISABLE.
Referenced by mainboard_smi_apmc().
Enable SMIs on writes to ACPI SMI command port.
Definition at line 76 of file smi_util.c.
References configure_smi(), HUDSON_SMI_ACPI_COMMAND, and SMI_MODE_SMI.
Referenced by hudson_init_acpi_ports().