coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_MEDIATEK_MT8195_GPIO_H
4 #define SOC_MEDIATEK_MT8195_GPIO_H
5 
6 #include <soc/addressmap.h>
7 #include <soc/gpio_common.h>
8 #include <types.h>
9 
10 enum {
11  MAX_GPIO_REG_BITS = 32,
12  MAX_GPIO_MODE_PER_REG = 8,
13  GPIO_MODE_BITS = 4,
14 };
15 
16 #define PIN(id, name, flag, bit, base, offset, \
17  func1, func2, func3, func4, func5, func6, func7) \
18  PAD_##name##_ID = id, \
19  PAD_##name##_FLAG = flag, \
20  PAD_##name##_BIT = bit, \
21  PAD_##name##_BASE = base, \
22  PAD_##name##_OFFSET = offset, \
23  PAD_##name##_FUNC_##func1 = 1, \
24  PAD_##name##_FUNC_##func2 = 2, \
25  PAD_##name##_FUNC_##func3 = 3, \
26  PAD_##name##_FUNC_##func4 = 4, \
27  PAD_##name##_FUNC_##func5 = 5, \
28  PAD_##name##_FUNC_##func6 = 6, \
29  PAD_##name##_FUNC_##func7 = 7
30 
31 #define GPIO(name) ((gpio_t){ \
32  .id = PAD_##name##_ID, \
33  .flag = PAD_##name##_FLAG, \
34  .bit = PAD_##name##_BIT, \
35  .base = PAD_##name##_BASE, \
36  .offset = PAD_##name##_OFFSET \
37  })
38 
39 enum {
40 
41  PIN(0, GPIO_00, 1, 0, 0x23, 0x60,
42  TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0,
43  PERSTN_1, IDDIG_1P, DMIC4_CLK),
44  PIN(1, GPIO_01, 1, 1, 0x23, 0x60,
45  TP_GPIO1_AO, MSDC2_CLK, TDMIN_DI, CLKM1,
46  CLKREQN_1, USB_DRVVBUS_1P, DMIC4_DAT),
47  PIN(2, GPIO_02, 1, 2, 0x23, 0x60,
48  TP_GPIO2_AO, MSDC2_DAT3, TDMIN_LRCK, CLKM2,
49  WAKEN_1, RES6, DMIC2_CLK),
50  PIN(3, GPIO_03, 1, 3, 0x23, 0x60,
51  TP_GPIO3_AO, MSDC2_DAT0, TDMIN_BCK, CLKM3,
52  RES5, RES6, DMIC2_DAT),
53  PIN(4, GPIO_04, 1, 4, 0x23, 0x60,
54  TP_GPIO4_AO, MSDC2_DAT2, SPDIF_IN1, UTXD3,
55  SDA2, RES6, IDDIG_2P),
56  PIN(5, GPIO_05, 1, 5, 0x23, 0x60,
57  TP_GPIO5_AO, MSDC2_DAT1, SPDIF_IN0, URXD3,
58  SCL2, RES6, USB_DRVVBUS_2P),
59  PIN(6, GPIO_06, 0, 0, 0x23, 0x70,
60  TP_GPIO6_AO, DP_TX_HPD, I2SO1_D4, UTXD4,
61  CMVREF3, RES6, DMIC3_CLK),
62  PIN(7, GPIO_07, 0, 1, 0x23, 0x70,
63  TP_GPIO7_AO, EDP_TX_HPD, I2SO1_D5, URXD4,
64  CMVREF4, RES6, DMIC3_DAT),
65  PIN(8, SDA0, 0, 7, 0x23, 0x70,
66  SDA0, PWM_0, RES3, SPDIF_OUT,
67  RES5, LVTS_FOUT, DBG_MON_A0),
68  PIN(9, SCL0, 0, 2, 0x23, 0x70,
69  SCL0, PWM_1, RES3, IR_IN,
70  RES5, LVTS_SDO, DBG_MON_A1),
71  PIN(10, SDA1, 0, 8, 0x23, 0x70,
72  SDA1, PWM_2, ADSP_URXD0, SPDIF_IN1,
73  RES5, LVTS_SCF, DBG_MON_A2),
74  PIN(11, SCL1, 0, 3, 0x23, 0x70,
75  SCL1, PWM_3, ADSP_UTXD0, SPDIF_IN0,
76  RES5, LVTS_SCK, DBG_MON_A3),
77  PIN(12, SDA2, 0, 9, 0x23, 0x70,
78  SDA2, DMIC3_DAT_R, I2SO1_D6, RES4,
79  RES5, LVTS_SDI, DBG_MON_A4),
80  PIN(13, SCL2, 0, 4, 0x23, 0x70,
81  SCL2, DMIC4_DAT_R, I2SO1_D7, RES4,
82  RES5, RES6, DBG_MON_A5),
83  PIN(14, SDA3, 0, 10, 0x23, 0x70,
84  SDA3, DMIC3_DAT, TDMIN_MCK, RES4,
85  RES5, RES6, DBG_MON_A6),
86  PIN(15, SCL3, 0, 5, 0x23, 0x70,
87  SCL3, DMIC3_CLK, TDMIN_DI, RES4,
88  RES5, RES6, DBG_MON_A7),
89  PIN(16, SDA4, 0, 11, 0x23, 0x70,
90  SDA4, DMIC4_DAT, TDMIN_LRCK, RES4,
91  RES5, RES6, DBG_MON_A8),
92  PIN(17, SCL4, 0, 6, 0x23, 0x70,
93  SCL4, DMIC4_CLK, TDMIN_BCK, RES4,
94  RES5, RES6, DBG_MON_A9),
95  PIN(18, DPTX_HPD, 0, 5, 0x10, 0x60,
96  DP_TX_HPD, RES2, RES3, RES4,
97  RES5, RES6, RES7),
98  PIN(19, PCIE_WAKE_N, 0, 12, 0x10, 0x60,
99  WAKEN, SCP_SDA1, MD32_0_JTAG_TCK, ADSP_JTAG0_TCK,
100  SDA6, RES6, RES7),
101  PIN(20, PCIE_PERESET_N, 0, 11, 0x10, 0x60,
102  PERSTN, SCP_SCL1, MD32_0_JTAG_TMS, ADSP_JTAG0_TMS,
103  SCL6, RES6, RES7),
104  PIN(21, PCIE_CLKREQ_N, 0, 10, 0x10, 0x60,
105  CLKREQN, RES2, MD32_0_JTAG_TDI, ADSP_JTAG0_TDI,
106  SCP_SDA1, RES6, RES7),
107  PIN(22, CMMCLK0, 0, 0, 0x10, 0x60,
108  CMMCLK0, PERSTN_1, RES3, RES4,
109  SCP_SCL1, RES6, MD32_0_GPIO0),
110  PIN(23, CMMCLK1, 0, 1, 0x10, 0x60,
111  CMMCLK1, CLKREQN_1, SDA4, DMIC1_CLK,
112  SCP_SDA0, RES6, MD32_0_GPIO1),
113  PIN(24, CMMCLK2, 0, 2, 0x10, 0x60,
114  CMMCLK2, WAKEN_1, SCL4, DMIC1_DAT,
115  SCP_SCL0, LVTS_26M, MD32_0_GPIO2),
116  PIN(25, CMMRST, 0, 4, 0x10, 0x60,
117  CMMRST, CMMCLK3, SPDIF_OUT, SDA6,
118  ADSP_JTAG0_TRSTN, MD32_0_JTAG_TRST, RES7),
119  PIN(26, CMMPDN, 0, 3, 0x10, 0x60,
120  CMMPDN, CMMCLK4, IR_IN, SCL6,
121  ADSP_JTAG0_TDO, MD32_0_JTAG_TDO, RES7),
122  PIN(27, HDMIRX_HTPLG, 0, 6, 0x10, 0x60,
123  HDMIRX20_HTPLG, CMFLASH0, MD32_0_TXD, TP_UTXD2_AO,
124  SCL7, UCTS2, DBG_MON_A18),
125  PIN(28, HDMIRX_PWR5V, 0, 7, 0x10, 0x60,
126  HDMIRX20_PWR5V, CMFLASH1, MD32_0_RXD, TP_URXD2_AO,
127  SDA7, URTS2, DBG_MON_A19),
128  PIN(29, HDMIRX_SCL, 0, 8, 0x10, 0x60,
129  HDMIRX20_SCL, CMFLASH2, SCL5, TP_URTS2_AO,
130  RES5, UTXD2, DBG_MON_A20),
131  PIN(30, HDMIRX_SDA, 0, 9, 0x10, 0x60,
132  HDMIRX20_SDA, CMFLASH3, SDA5, TP_UCTS2_AO,
133  RES5, URXD2, DBG_MON_A21),
134  PIN(31, HDMITX_PWR5V, 0, 13, 0x21, 0xa0,
135  HDMITX20_PWR5V, DMIC1_DAT_R, PERSTN, RES4,
136  RES5, RES6, DBG_MON_A22),
137  PIN(32, HDMITX_HTPLG, 0, 12, 0x21, 0xa0,
138  HDMITX20_HTPLG, RES2, CLKREQN, RES4,
139  RES5, RES6, DBG_MON_A23),
140  PIN(33, HDMITX_CEC, 0, 11, 0x21, 0xa0,
141  HDMITX20_CEC, CMVREF0, WAKEN, RES4,
142  RES5, RES6, RES7),
143  PIN(34, HDMITX_SCL, 0, 14, 0x21, 0xa0,
144  HDMITX20_SCL, CMVREF1, SCL7, SCL6,
145  RES5, RES6, DBG_MON_A24),
146  PIN(35, HDMITX_SDA, 0, 15, 0x21, 0xa0,
147  HDMITX20_SDA, CMVREF2, SDA7, SDA6,
148  RES5, RES6, DBG_MON_A25),
149  PIN(36, PMIC_RTC32K_CK, 0, 3, 0x21, 0xb0,
150  RTC32K_CK, RES2, RES3, RES4,
151  RES5, RES6, DBG_MON_A27),
152  PIN(37, PMIC_WATCHDOG, 0, 6, 0x21, 0xb0,
153  WATCHDOG, RES2, RES3, RES4,
154  RES5, RES6, DBG_MON_A28),
155  PIN(38, PMIC_SRCLKEN_IN0, 0, 4, 0x21, 0xb0,
156  SRCLKENA0, RES2, RES3, RES4,
157  RES5, RES6, DBG_MON_A29),
158  PIN(39, PMIC_SRCLKEN_IN1, 0, 5, 0x21, 0xb0,
159  SRCLKENA1, DMIC2_DAT_R, RES3, RES4,
160  RES5, RES6, DBG_MON_A30),
161  PIN(40, PWRAP_SPI_CSN, 0, 8, 0x21, 0xb0,
162  PWRAP_SPI0_CSN, RES2, SPIM3_CSB, RES4,
163  RES5, RES6, DBG_MON_A31),
164  PIN(41, PWRAP_SPI_CK, 0, 7, 0x21, 0xb0,
165  PWRAP_SPI0_CK, RES2, SPIM3_CLK, RES4,
166  RES5, RES6, DBG_MON_A32),
167  PIN(42, PWRAP_SPI_MO, 0, 10, 0x21, 0xb0,
168  PWRAP_SPI0_MO, PWRAP_SPI0_MI, SPIM3_MO, RES4,
169  RES5, RES6, DBG_MON_B0),
170  PIN(43, PWRAP_SPI_MI, 0, 9, 0x21, 0xb0,
171  PWRAP_SPI0_MI, PWRAP_SPI0_MO, SPIM3_MI, RES4,
172  RES5, RES6, DBG_MON_B1),
173  PIN(44, SPMI_M_SCL, 0, 21, 0x21, 0xb0,
174  SPMI_M_SCL, I2SI00_DATA1, SCL5, UTXD5,
175  RES5, RES6, DBG_MON_B2),
176  PIN(45, SPMI_M_SDA, 0, 22, 0x21, 0xb0,
177  SPMI_M_SDA, I2SI00_DATA2, SDA5, URXD5,
178  RES5, RES6, DBG_MON_B3),
179  PIN(46, I2SIN_MCK, 0, 18, 0x21, 0xa0,
180  I2SIN_MCK, I2SI00_DATA3, SPLIN_MCK, RES4,
181  RES5, RES6, DBG_MON_B4),
182  PIN(47, I2SIN_BCK, 0, 16, 0x21, 0xa0,
183  I2SIN_BCK, I2SIN0_BCK, SPLIN_LRCK, RES4,
184  RES5, RES6, DBG_MON_B5),
185  PIN(48, I2SIN_WS, 0, 19, 0x21, 0xa0,
186  I2SIN_WS, I2SIN0_LRCK, SPLIN_BCK, RES4,
187  RES5, RES6, DBG_MON_B6),
188  PIN(49, I2SIN_D0, 0, 17, 0x21, 0xa0,
189  I2SIN_D0, I2SI00_DATA0, SPLIN_D0, RES4,
190  RES5, RES6, DBG_MON_B7),
191  PIN(50, I2SO1_MCK, 0, 25, 0x21, 0xa0,
192  I2SO1_MCK, I2SI5_D0, RES3, I2SO4_MCK,
193  RES5, RES6, DBG_MON_B8),
194  PIN(51, I2SO1_BCK, 0, 20, 0x21, 0xa0,
195  I2SO1_BCK, I2SI5_BCK, RES3, RES4,
196  RES5, RES6, DBG_MON_B9),
197  PIN(52, I2SO1_WS, 0, 26, 0x21, 0xa0,
198  I2SO1_WS, I2SI5_WS, RES3, RES4,
199  RES5, RES6, DBG_MON_B10),
200  PIN(53, I2SO1_D0, 0, 21, 0x21, 0xa0,
201  I2SO1_D0, I2SI5_MCK, RES3, RES4,
202  RES5, RES6, DBG_MON_B11),
203  PIN(54, I2SO1_D1, 0, 22, 0x21, 0xa0,
204  I2SO1_D1, I2SI01_DATA1, SPLIN_D1, I2SO4_BCK,
205  RES5, RES6, DBG_MON_B12),
206  PIN(55, I2SO1_D2, 0, 23, 0x21, 0xa0,
207  I2SO1_D2, I2SI01_DATA2, SPLIN_D2, I2SO4_WS,
208  RES5, RES6, DBG_MON_B13),
209  PIN(56, I2SO1_D3, 0, 24, 0x21, 0xa0,
210  I2SO1_D3, I2SI01_DATA3, SPLIN_D3, I2SO4_D0,
211  RES5, RES6, DBG_MON_B14),
212  PIN(57, I2SO2_MCK, 0, 29, 0x21, 0xa0,
213  I2SO2_MCK, I2SO1_D12, LCM1_RST, RES4,
214  RES5, RES6, DBG_MON_B15),
215  PIN(58, I2SO2_BCK, 0, 27, 0x21, 0xa0,
216  I2SO2_BCK, I2SO1_D13, I2SIN1_BCK, RES4,
217  RES5, RES6, DBG_MON_B16),
218  PIN(59, I2SO2_WS, 0, 30, 0x21, 0xa0,
219  I2SO2_WS, I2SO1_D14, I2SIN1_LRCK, RES4,
220  RES5, RES6, DBG_MON_B17),
221  PIN(60, I2SO2_D0, 0, 28, 0x21, 0xa0,
222  I2SO2_D0, I2SO1_D15, I2SI01_DATA0, RES4,
223  RES5, RES6, DBG_MON_B18),
224  PIN(61, DMIC1_SCK, 0, 8, 0x21, 0xa0,
225  DMIC1_CLK, I2SO2_BCK, SCP_SPI2_CK, RES4,
226  RES5, RES6, DBG_MON_B19),
227  PIN(62, DMIC1_DAT, 0, 7, 0x21, 0xa0,
228  DMIC1_DAT, I2SO2_WS, SCP_SPI2_MI, RES4,
229  RES5, RES6, DBG_MON_B20),
230  PIN(63, DMIC2_SCK, 0, 10, 0x21, 0xa0,
231  DMIC2_CLK, VBUSVALID, SCP_SPI2_MO, SCP_SCL2,
232  SCP_JTAG1_TDO, JTDO_SEL1, DBG_MON_B21),
233  PIN(64, DMIC2_DAT, 0, 9, 0x21, 0xa0,
234  DMIC2_DAT, VBUSVALID_1P, SCP_SPI2_CS, SCP_SDA2,
235  RES5, RES6, DBG_MON_B22),
236  PIN(65, PCM_DO, 0, 1, 0x21, 0xb0,
237  PCM_DO, AUXIF_ST0, UCTS2, RES4,
238  SCP_JTAG1_TMS, JTMS_SEL1, DBG_MON_B23),
239  PIN(66, PCM_CLK, 0, 31, 0x21, 0xa0,
240  PCM_CLK, AUXIF_CLK0, URTS2, RES4,
241  SCP_JTAG1_TCK, JTCK_SEL1, DBG_MON_B24),
242  PIN(67, PCM_DI, 0, 0, 0x21, 0xb0,
243  PCM_DI, AUXIF_ST1, UTXD2, RES4,
244  SCP_JTAG1_TRSTN, JTRSTn_SEL1, DBG_MON_B25),
245  PIN(68, PCM_SYNC, 0, 2, 0x21, 0xb0,
246  PCM_SYNC, AUXIF_CLK1, URXD2, RES4,
247  SCP_JTAG1_TDI, JTDI_SEL1, DBG_MON_B26),
248  PIN(69, AUD_CLK_MOSI, 0, 0, 0x21, 0xa0,
249  AUD_CLK_MOSI, I2SIN2_BCK, PWM_0, WAKEN,
250  RES5, RES6, DBG_MON_B27),
251  PIN(70, AUD_SYNC_MOSI, 0, 6, 0x21, 0xa0,
252  AUD_SYNC_MOSI, I2SIN2_LRCK, PWM_1, PERSTN,
253  RES5, RES6, DBG_MON_B28),
254  PIN(71, AUD_DAT_MOSI0, 0, 4, 0x21, 0xa0,
255  AUD_DAT_MOSI0, IDDIG_2P, PWM_2, CLKREQN,
256  RES5, RES6, DBG_MON_B29),
257  PIN(72, AUD_DAT_MOSI1, 0, 5, 0x21, 0xa0,
258  AUD_DAT_MOSI1, USB_DRVVBUS_2P, PWM_3, PERSTN_1,
259  RES5, RES6, DBG_MON_B30),
260  PIN(73, AUD_DAT_MISO0, 0, 1, 0x21, 0xa0,
261  AUD_DAT_MISO0, I2SI02_DATA0, RES3, CLKREQN_1,
262  VOW_DAT_MISO, RES6, DBG_MON_B31),
263  PIN(74, AUD_DAT_MISO1, 0, 2, 0x21, 0xa0,
264  AUD_DAT_MISO1, I2SI02_DATA1, RES3, WAKEN_1,
265  VOW_CLK_MISO, RES6, DBG_MON_B32),
266  PIN(75, AUD_DAT_MISO2, 0, 3, 0x21, 0xa0,
267  AUD_DAT_MISO2, I2SI02_DATA2, RES3, RES4,
268  RES5, RES6, RES7),
269  PIN(76, SCP_VREQ_VAO, 0, 11, 0x21, 0xb0,
270  SCP_VREQ_VAO, I2SI02_DATA3, RES3, RES4,
271  RES5, RES6, DBG_MON_A26),
272  PIN(77, DGI_D0, 1, 1, 0x22, 0x60,
273  DGI_D0, DPI_D0, I2SI4_MCK, SPIM4_CLK,
274  GBE_TXD3, SPM_JTAG_TCK, RES7),
275  PIN(78, DGI_D1, 1, 2, 0x22, 0x60,
276  DGI_D1, DPI_D1, I2SI4_BCK, SPIM4_MO,
277  GBE_TXD2, SPM_JTAG_TMS, RES7),
278  PIN(79, DGI_D2, 1, 9, 0x22, 0x60,
279  DGI_D2, DPI_D2, I2SI4_WS, SPIM4_CSB,
280  GBE_TXD1, SPM_JTAG_TDI, RES7),
281  PIN(80, DGI_D3, 1, 10, 0x22, 0x60,
282  DGI_D3, DPI_D3, I2SI4_D0, SPIM4_MI,
283  GBE_TXD0, SPM_JTAG_TDO, RES7),
284  PIN(81, DGI_D4, 1, 11, 0x22, 0x60,
285  DGI_D4, DPI_D4, I2SI5_MCK, SPIM5_CLK,
286  GBE_RXD3, SPM_JTAG_TRSTN, RES7),
287  PIN(82, DGI_D5, 1, 12, 0x22, 0x60,
288  DGI_D5, DPI_D5, I2SI5_BCK, SPIM5_MO,
289  GBE_RXD2, MCUPM_JTAG_TDO, RES7),
290  PIN(83, DGI_D6, 1, 13, 0x22, 0x60,
291  DGI_D6, DPI_D6, I2SI5_WS, SPIM5_CSB,
292  GBE_RXD1, MCUPM_JTAG_TMS, RES7),
293  PIN(84, DGI_D7, 1, 14, 0x22, 0x60,
294  DGI_D7, DPI_D7, I2SI5_D0, SPIM5_MI,
295  GBE_RXD0, MCUPM_JTAG_TCK, RES7),
296  PIN(85, DGI_D8, 1, 15, 0x22, 0x60,
297  DGI_D8, DPI_D8, I2SO4_MCK, SCP_SPI1_B_CK,
298  GBE_TXC, MCUPM_JTAG_TDI, RES7),
299  PIN(86, DGI_D9, 1, 16, 0x22, 0x60,
300  DGI_D9, DPI_D9, I2SO4_BCK, SCP_SPI1_B_MI,
301  GBE_RXC, MCUPM_JTAG_TRSTN, RES7),
302  PIN(87, DGI_D10, 1, 3, 0x22, 0x60,
303  DGI_D10, DPI_D10, I2SO4_WS, SCP_SPI1_B_CS,
304  GBE_RXDV, SSPM_JTAG_TDO, RES7),
305  PIN(88, DGI_D11, 1, 4, 0x22, 0x60,
306  DGI_D11, DPI_D11, I2SO4_D0, SCP_SPI1_B_MO,
307  GBE_TXEN, SSPM_JTAG_TMS, RES7),
308  PIN(89, DGI_D12, 1, 5, 0x22, 0x60,
309  DGI_D12, DPI_D12, MSDC2_CMD_A, I2SO5_BCK,
310  GBE_MDC, SSPM_JTAG_TCK, RES7),
311  PIN(90, DGI_D13, 1, 6, 0x22, 0x60,
312  DGI_D13, DPI_D13, MSDC2_CLK_A, I2SO5_WS,
313  GBE_MDIO, SSPM_JTAG_TDI, RES7),
314  PIN(91, DGI_D14, 1, 7, 0x22, 0x60,
315  DGI_D14, DPI_D14, MSDC2_DAT3_A, I2SO5_D0,
316  GBE_TXER, SSPM_JTAG_TRSTN, RES7),
317  PIN(92, DGI_D15, 1, 8, 0x22, 0x60,
318  DGI_D15, DPI_D15, MSDC2_DAT0_A, I2SO2_D1,
319  GBE_RXER, CCU0_JTAG_TDO, RES7),
320  PIN(93, DGI_HSYNC, 1, 18, 0x22, 0x60,
321  DGI_HSYNC, DPI_HSYNC, MSDC2_DAT2_A, I2SO2_D2,
322  GBE_COL, CCU0_JTAG_TMS, RES7),
323  PIN(94, DGI_VSYNC, 1, 19, 0x22, 0x60,
324  DGI_VSYNC, DPI_VSYNC, MSDC2_DAT1_A, I2SO2_D3,
325  GBE_INTR, CCU0_JTAG_TDI, RES7),
326  PIN(95, DGI_DE, 1, 17, 0x22, 0x60,
327  DGI_DE, DPI_DE, UTXD2, RES4,
328  I2SIN_D1, CCU0_JTAG_TCK, RES7),
329  PIN(96, DGI_CK, 1, 0, 0x22, 0x60,
330  DGI_CK, DPI_CK, URXD2, I2SO5_MCK,
331  I2SIN_D2, CCU0_JTAG_TRST, RES7),
332  PIN(97, DISP_PWM0, 0, 0, 0x22, 0x70,
333  DISP_PWM0, DVFSRC_EXT_REQ, RES3, RES4,
334  RES5, RES6, RES7),
335  PIN(98, UART0_TXD, 0, 4, 0x22, 0x70,
336  UTXD0, RES2, RES3, RES4,
337  RES5, RES6, RES7),
338  PIN(99, UART0_RXD, 0, 3, 0x22, 0x70,
339  URXD0, RES2, RES3, RES4,
340  RES5, RES6, RES7),
341  PIN(100, UART1_RTS, 0, 6, 0x22, 0x70,
342  URTS1, DSI_TE, I2SO1_D8, KPROW2,
343  PWM_0, TP_URTS1_AO, I2SIN_D0),
344  PIN(101, UART1_CTS, 0, 5, 0x22, 0x70,
345  UCTS1, DSI1_TE, I2SO1_D9, KPCOL2,
346  PWM_1, TP_UCTS1_AO, I2SIN_D1),
347  PIN(102, UART1_TXD, 0, 8, 0x22, 0x70,
348  UTXD1, VBUSVALID_2P, I2SO1_D10, SSPM_UTXD_AO,
349  TP_UTXD1_AO, MD32_1_TXD, I2SIN_D2),
350  PIN(103, UART1_RXD, 0, 7, 0x22, 0x70,
351  URXD1, VBUSVALID_3P, I2SO1_D11, SSPM_URXD_AO,
352  TP_URXD1_AO, MD32_1_RXD, I2SIN_D3),
353  PIN(104, KPROW0, 1, 22, 0x22, 0x60,
354  KPROW0, DISP_PWM1, RES3, RES4,
355  RES5, RES6, RES7),
356  PIN(105, KPROW1, 1, 23, 0x22, 0x60,
357  KPROW1, EDP_TX_HPD, PWM_2, RES4,
358  RES5, RES6, RES7),
359  PIN(106, KPCOL0, 1, 20, 0x22, 0x60,
360  KPCOL0, RES2, RES3, RES4,
361  RES5, RES6, RES7),
362  PIN(107, KPCOL1, 1, 21, 0x22, 0x60,
363  KPCOL1, DSI1_TE, PWM_3, SCP_SCL3,
364  I2SIN_MCK, RES6, RES7),
365  PIN(108, DSI_LCM_RST, 0, 2, 0x22, 0x70,
366  LCM_RST, KPCOL1, RES3, SCP_SDA3,
367  I2SIN_BCK, RES6, RES7),
368  PIN(109, DSI_DSI_TE, 0, 1, 0x22, 0x70,
369  DSI_TE, I2SIN_D3, RES3, RES4,
370  I2SIN_WS, RES6, RES7),
371  PIN(110, MSDC1_CMD, 1, 1, 0x14, 0x20,
372  MSDC1_CMD, JTMS_SEL3, UDI_TMS, RES4,
373  CCU1_JTAG_TMS, IPU_JTAG_TMS, RES7),
374  PIN(111, MSDC1_CLK, 1, 0, 0x14, 0x20,
375  MSDC1_CLK, JTCK_SEL3, UDI_TCK, RES4,
376  CCU1_JTAG_TCK, IPU_JTAG_TCK, RES7),
377  PIN(112, MSDC1_DAT0, 1, 2, 0x14, 0x20,
378  MSDC1_DAT0, JTDI_SEL3, UDI_TDI, I2SO2_D0,
379  CCU1_JTAG_TDI, IPU_JTAG_TDI, RES7),
380  PIN(113, MSDC1_DAT1, 1, 3, 0x14, 0x20,
381  MSDC1_DAT1, JTDO_SEL3, UDI_TDO, I2SO2_D1,
382  CCU1_JTAG_TDO, IPU_JTAG_TDO, RES7),
383  PIN(114, MSDC1_DAT2, 1, 4, 0x14, 0x20,
384  MSDC1_DAT2, JTRSTn_SEL3, UDI_NTRST, I2SO2_D2,
385  CCU1_JTAG_TRST, IPU_JTAG_TRST, RES7),
386  PIN(115, MSDC1_DAT3, 1, 5, 0x14, 0x20,
387  MSDC1_DAT3, RES2, RES3, I2SO2_D3,
388  RES5, MD32_1_GPIO2, RES7),
389  PIN(116, EMMC_DAT7, 1, 9, 0x25, 0x50,
390  MSDC0_DAT7, RES2, RES3, RES4,
391  RES5, RES6, RES7),
392  PIN(117, EMMC_DAT6, 1, 8, 0x25, 0x50,
393  MSDC0_DAT6, RES2, RES3, RES4, RES5, RES6, RES7),
394  PIN(118, EMMC_DAT5, 1, 7, 0x25, 0x50,
395  MSDC0_DAT5, RES2, RES3, RES4,
396  RES5, RES6, RES7),
397  PIN(119, EMMC_DAT4, 1, 6, 0x25, 0x50,
398  MSDC0_DAT4, RES2, RES3, RES4,
399  RES5, RES6, RES7),
400  PIN(120, EMMC_RSTB, 1, 11, 0x25, 0x50,
401  MSDC0_RSTB, RES2, RES3, RES4,
402  RES5, RES6, RES7),
403  PIN(121, EMMC_CMD, 1, 1, 0x25, 0x50,
404  MSDC0_CMD, RES2, RES3, RES4,
405  RES5, RES6, RES7),
406  PIN(122, EMMC_CLK, 1, 0, 0x25, 0x50,
407  MSDC0_CLK, RES2, RES3, RES4,
408  RES5, RES6, RES7),
409  PIN(123, EMMC_DAT3, 1, 5, 0x25, 0x50,
410  MSDC0_DAT3, RES2, RES3, RES4,
411  RES5, RES6, RES7),
412  PIN(124, EMMC_DAT2, 1, 4, 0x25, 0x50,
413  MSDC0_DAT2, RES2, RES3, RES4,
414  RES5, RES6, RES7),
415  PIN(125, EMMC_DAT1, 1, 3, 0x25, 0x50,
416  MSDC0_DAT1, RES2, RES3, RES4,
417  RES5, RES6, RES7),
418  PIN(126, EMMC_DAT0, 1, 2, 0x25, 0x50,
419  MSDC0_DAT0, RES2, RES3, RES4,
420  RES5, RES6, RES7),
421  PIN(127, EMMC_DSL, 1, 10, 0x25, 0x50,
422  MSDC0_DSL, RES2, RES3, RES4,
423  RES5, RES6, RES7),
424  PIN(128, USB_IDDIG, 0, 11, 0x22, 0x70,
425  IDDIG, UCTS2, UTXD5, UFS_MPHY_SCL,
426  mbistreaden_trigger, MD32_1_GPIO0, SCP_SCL2),
427  PIN(129, USB_DRV_VBUS, 0, 9, 0x22, 0x70,
428  SB_DRVVBUS, URTS2, URXD5, UFS_MPHY_SDA,
429  mbistwriteen_trigger, MD32_1_GPIO1, SCP_SDA2),
430  PIN(130, USB_IDDIG_1P, 0, 12, 0x22, 0x70,
431  IDDIG_1P, SPINOR_IO2, SNFI_WP, VPU_UDI_NTRST,
432  RES5, RES6, RES7),
433  PIN(131, USB_DRV_VBUS_1P, 0, 10, 0x22, 0x70,
434  USB_DRVVBUS_1P, SPINOR_IO3, SNFI_HOLD, MD32_1_JTAG_TRST,
435  SCP_JTAG0_TRSTN, APU_JTAG_TRST, RES7),
436  PIN(132, SPIM0_CSB, 0, 1, 0x25, 0x60,
437  SPIM0_CSB, SCP_SPI0_CS, SPIS0_CSB, VPU_UDI_TMS,
438  RES5, I2SO5_D0, RES7),
439  PIN(133, SPIM0_CLK, 0, 0, 0x25, 0x60,
440  SPIM0_CLK, SCP_SPI0_CK, SPIS0_CLK, VPU_UDI_TCK,
441  RES5, I2SO5_BCK, RES7),
442  PIN(134, SPIM0_MO, 0, 3, 0x25, 0x60,
443  SPIM0_MO, SCP_SPI0_MO, SPIS0_SI, VPU_UDI_TDO,
444  RES5, I2SO5_WS, RES7),
445  PIN(135, SPIM0_MI, 0, 2, 0x25, 0x60,
446  SPIM0_MI, SCP_SPI0_MI, SPIS0_SO, VPU_UDI_TDI,
447  RES5, I2SO5_MCK, RES7),
448  PIN(136, SPIM1_CSB, 0, 14, 0x21, 0xb0,
449  SPIM1_CSB, SCP_SPI1_A_CS, SPIS1_CSB, MD32_1_JTAG_TMS,
450  SCP_JTAG0_TMS, APU_JTAG_TMS, DBG_MON_A15),
451  PIN(137, SPIM1_CLK, 0, 13, 0x21, 0xb0,
452  SPIM1_CLK, SCP_SPI1_A_CK, SPIS1_CLK, MD32_1_JTAG_TCK,
453  SCP_JTAG0_TCK, APU_JTAG_TCK, DBG_MON_A14),
454  PIN(138, SPIM1_MO, 0, 16, 0x21, 0xb0,
455  SPIM1_MO, SCP_SPI1_A_MO, SPIS1_SI, MD32_1_JTAG_TDO,
456  SCP_JTAG0_TDO, APU_JTAG_TDO, DBG_MON_A16),
457  PIN(139, SPIM1_MI, 0, 15, 0x21, 0xb0,
458  SPIM1_MI, SCP_SPI1_A_MI, SPIS1_SO, MD32_1_JTAG_TDI,
459  SCP_JTAG0_TDI, APU_JTAG_TDI, DBG_MON_A17),
460  PIN(140, SPIM2_CSB, 0, 18, 0x21, 0xb0,
461  SPIM2_CSB, SPINOR_CS, SNFI_CS, DMIC3_DAT,
462  RES5, RES6, DBG_MON_A11),
463  PIN(141, SPIM2_CLK, 0, 17, 0x21, 0xb0,
464  SPIM2_CLK, SPINOR_CK, SNFI_CLK, DMIC3_CLK,
465  RES5, RES6, DBG_MON_A10),
466  PIN(142, SPIM2_MO, 0, 20, 0x21, 0xb0,
467  SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT,
468  RES5, RES6, DBG_MON_A12),
469  PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0,
470  PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK,
471  RES5, RES6, DBG_MON_A13),
472 };
473 
474 struct val_regs {
475  uint32_t val;
476  uint32_t set;
477  uint32_t rst;
478  uint32_t align;
479 };
480 
481 struct gpio_regs {
482  struct val_regs dir[7];
483  uint8_t rsv00[144];
484  struct val_regs dout[7];
485  uint8_t rsv01[144];
486  struct val_regs din[7];
487  uint8_t rsv02[144];
488  struct val_regs mode[28];
489  uint8_t rsv03[560];
490  uint32_t dram_pinmux_trapping;
491 };
492 
493 check_member(gpio_regs, mode[27].val, 0x4b0);
494 check_member(gpio_regs, dram_pinmux_trapping, 0x6f0);
495 
496 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
497 
498 #endif
SPDIF_OUT
@ SPDIF_OUT
Definition: azalia_device.h:82
GPIO_BASE
#define GPIO_BASE
Definition: lpc.h:21
check_member
check_member(gpio_regs, msdc2_ctrl5, 0xcb0)
MAX_GPIO_MODE_PER_REG
@ MAX_GPIO_MODE_PER_REG
Definition: gpio.h:11
GPIO_MODE_BITS
@ GPIO_MODE_BITS
Definition: gpio.h:12
MAX_GPIO_REG_BITS
@ MAX_GPIO_REG_BITS
Definition: gpio.h:10
mtk_gpio
static struct gpio_regs *const mtk_gpio
Definition: gpio.h:496
PIN
#define PIN(id, name, flag, bit, base, offset, func1, func2, func3, func4, func5, func6, func7)
Definition: gpio.h:16
uint32_t
unsigned int uint32_t
Definition: stdint.h:14
uint8_t
unsigned char uint8_t
Definition: stdint.h:8
gpio_regs
Definition: gpio.h:312
gpio_regs::din
struct val_regs din[9]
Definition: gpio.h:322
gpio_regs::rsv00
uint8_t rsv00[112]
Definition: gpio.h:314
gpio_regs::mode
struct val_regs mode[27]
Definition: gpio.h:324
gpio_regs::rsv03
uint8_t rsv03[256]
Definition: gpio.h:319
gpio_regs::rsv02
uint8_t rsv02[112]
Definition: gpio.h:318
gpio_regs::dout
struct val_regs dout[9]
Definition: gpio.h:320
gpio_regs::rsv01
uint8_t rsv01[112]
Definition: gpio.h:316
gpio_regs::dram_pinmux_trapping
uint32_t dram_pinmux_trapping
Definition: gpio.h:631
gpio_regs::dir
struct val_regs dir[9]
Definition: gpio.h:313
val_regs
Definition: gpio.h:305
val_regs::align
uint32_t align
Definition: gpio.h:309
val_regs::set
uint32_t set
Definition: gpio.h:307
val_regs::val
uint32_t val
Definition: gpio.h:306
val_regs::rst
uint32_t rst
Definition: gpio.h:308
val
u8 val
Definition: sys.c:300