coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
gpio.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * This file is created based on MT8186 Functional Specification
5  * Chapter number: 5.1
6  */
7 
8 #ifndef SOC_MEDIATEK_MT8186_GPIO_H
9 #define SOC_MEDIATEK_MT8186_GPIO_H
10 
11 #include <soc/addressmap.h>
12 #include <soc/gpio_common.h>
13 #include <types.h>
14 
15 #define GPIO_NUM 185
16 
17 enum {
21 };
22 
23 enum gpio_drv {
32 };
33 
34 #define PIN(id, name, flag, bit, base, offset, \
35  func1, func2, func3, func4, func5, func6, func7) \
36  PAD_##name##_ID = id, \
37  PAD_##name##_FLAG = flag, \
38  PAD_##name##_BIT = bit, \
39  PAD_##name##_BASE = base, \
40  PAD_##name##_OFFSET = offset, \
41  PAD_##name##_FUNC_##func1 = 1, \
42  PAD_##name##_FUNC_##func2 = 2, \
43  PAD_##name##_FUNC_##func3 = 3, \
44  PAD_##name##_FUNC_##func4 = 4, \
45  PAD_##name##_FUNC_##func5 = 5, \
46  PAD_##name##_FUNC_##func6 = 6, \
47  PAD_##name##_FUNC_##func7 = 7
48 
49 #define GPIO(name) ((gpio_t){ \
50  .id = PAD_##name##_ID, \
51  .flag = PAD_##name##_FLAG, \
52  .bit = PAD_##name##_BIT, \
53  .base = PAD_##name##_BASE, \
54  .offset = PAD_##name##_OFFSET \
55  })
56 
57 enum {
58  PIN(0, EINT0, 0, 13, 0x16, 0x50,
59  I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0,
60  SCP_SPI0_CK, TP_GPIO0_AO, dbg_mon_a0),
61  PIN(1, EINT1, 0, 14, 0x16, 0x50,
62  I2S0_BCK, SPI0_CSB_B, I2S2_BCK, CMFLASH1,
63  SCP_SPI0_CS, TP_GPIO1_AO, RES7),
64  PIN(2, EINT2, 0, 17, 0x16, 0x50,
65  I2S0_LRCK, SPI0_MO_B, I2S2_LRCK, CMFLASH2,
66  SCP_SPI0_MO, TP_GPIO2_AO, RES7),
67  PIN(3, EINT3, 0, 18, 0x16, 0x50,
68  I2S0_DI, SPI0_MI_B, I2S2_DI, SRCLKENAI1,
69  SCP_SPI0_MI, TP_GPIO3_AO, RES7),
70  PIN(4, EINT4, 0, 19, 0x16, 0x50,
71  I2S3_DO, RES2, I2S1_DO, RES4,
72  RES5, TP_GPIO4_AO, RES7),
73  PIN(5, EINT5, 0, 20, 0x16, 0x50,
74  EXT_FRAME_SYNC, RES2, RES3, RES4,
75  RES5, TP_GPIO5_AO, RES7),
76  PIN(6, EINT6, 0, 19, 0x24, 0x60,
77  I2S3_MCK, SPI1_CLK_B, I2S1_MCK, DPI_DATA22,
78  RES5, TP_GPIO6_AO, RES7),
79  PIN(7, EINT7, 0, 20, 0x24, 0x60,
80  I2S3_BCK, SPI1_CSB_B, I2S1_BCK, DPI_DATA23,
81  RES5, TP_GPIO7_AO, RES7),
82  PIN(8, EINT8, 0, 21, 0x24, 0x60,
83  I2S3_LRCK, SPI1_MO_B, I2S1_LRCK, CONN_UART0_RXD,
84  SSPM_URXD_AO, ADSP_UART_RX, CONN_MCU_DBGACK_N),
85  PIN(9, EINT9, 0, 22, 0x24, 0x60,
86  I2S3_DO, SPI1_MI_B, I2S1_DO, CONN_UART0_TXD,
87  SSPM_UTXD_AO, ADSP_UART_TX, CONN_MCU_DBGI_N),
88  PIN(10, EINT10, 0, 16, 0x24, 0x60,
89  I2S0_MCK, SPI4_CLK_A, I2S2_MCK, SPM_JTAG_TDI,
90  SCP_JTAG_TDI, ADSP_JTAG_TDI, CONN_MCU_TDI),
91  PIN(11, EINT11, 0, 17, 0x24, 0x60,
92  I2S0_BCK, SPI4_CSB_A, I2S2_BCK, SPM_JTAG_TRSTN,
93  SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, CONN_MCU_TRST_B),
94  PIN(12, EINT12, 0, 18, 0x24, 0x60,
95  I2S0_LRCK, SPI4_MO_A, I2S2_LRCK, SPM_JTAG_TCK,
96  SCP_JTAG_TCK, ADSP_JTAG_TCK, CONN_MCU_TCK),
97  PIN(13, EINT13, 0, 0, 0x23, 0x80,
98  I2S0_DI, SPI4_MI_A, I2S2_DI, SPM_JTAG_TDO,
99  SCP_JTAG_TDO, ADSP_JTAG_TDO, CONN_MCU_TDO),
100  PIN(14, EINT14, 0, 1, 0x23, 0x80,
101  RES1, RES2, CLKM0, SPM_JTAG_TMS,
102  SCP_JTAG_TMS, ADSP_JTAG_TMS, CONN_MCU_TMS),
103  PIN(15, EINT15, 0, 15, 0x16, 0x50,
104  EXT_FRAME_SYNC, SRCLKENAI1, CLKM1, PWM0,
105  RES5, RES6, RES7),
106  PIN(16, EINT16, 0, 16, 0x16, 0x50,
107  CONN_WIFI_TXD, SRCLKENAI0, CLKM2, PWM1,
108  RES5, RES6, RES7),
109  PIN(17, EINT17, 0, 9, 0x25, 0x90,
110  RES1, RES2, CLKM3, PWM2,
111  RES5, RES6, dbg_mon_a32),
112  PIN(18, EINT18, 0, 10, 0x25, 0x90,
113  RES1, CMVREF0, RES3, RES4,
114  RES5, SPI2_CLK_B, dbg_mon_a26),
115  PIN(19, CAM_PDN0, 0, 3, 0x25, 0x90,
116  RES1, CMVREF1, RES3, RES4,
117  ANT_SEL3, SPI2_CSB_B, dbg_mon_a2),
118  PIN(20, CAM_RST0, 0, 6, 0x25, 0x90,
119  RES1, CMVREF2, RES3, RES4,
120  ANT_SEL4, SPI2_MO_B, dbg_mon_a3),
121  PIN(21, CAM_PDN1, 0, 4, 0x25, 0x90,
122  I2S0_MCK, I2S1_MCK, I2S3_MCK, RES4,
123  ANT_SEL5, SPI2_MI_B, dbg_mon_a4),
124  PIN(22, CAM_RST1, 0, 7, 0x25, 0x90,
125  I2S0_BCK, I2S1_BCK, I2S3_BCK, TDM_RX_LRCK,
126  ANT_SEL6, RES6, dbg_mon_a5),
127  PIN(23, CAM_PDN2, 0, 5, 0x25, 0x90,
128  I2S0_LRCK, I2S1_LRCK, I2S3_LRCK, TDM_RX_BCK,
129  ANT_SEL7, RES6, dbg_mon_a6),
130  PIN(24, CAM_RST2, 0, 8, 0x25, 0x90,
131  I2S0_DI, I2S1_DO, I2S3_DO, TDM_RX_MCK,
132  RES5, RES6, dbg_mon_a7),
133  PIN(25, I2S2_MCK, 0, 18, 0x25, 0x90,
134  I2S2_MCK, PCM_CLK, SPI4_CLK_B, TDM_RX_DATA0,
135  RES5, RES6, dbg_mon_a8),
136  PIN(26, I2S2_BCK, 0, 15, 0x25, 0x90,
137  I2S2_BCK, PCM_SYNC, SPI4_CSB_B, TDM_RX_DATA1,
138  RES5, RES6, dbg_mon_a9),
139  PIN(27, I2S2_LRCK, 0, 17, 0x25, 0x90,
140  I2S2_LRCK, PCM_DI, SPI4_MO_B, TDM_RX_DATA2,
141  RES5, RES6, dbg_mon_a10),
142  PIN(28, I2S2_DI, 0, 16, 0x25, 0x90,
143  I2S2_DI, PCM_DO, SPI4_MI_B, TDM_RX_DATA3,
144  RES5, RES6, RES7),
145  PIN(29, ANT_SEL0, 0, 0, 0x16, 0x50,
146  ANT_SEL0, GPS_L1_ELNA_EN, RES3, RES4,
147  RES5, RES6, RES7),
148  PIN(30, ANT_SEL1, 0, 1, 0x16, 0x50,
149  ANT_SEL1, RES2, RES3, RES4,
150  RES5, RES6, RES7),
151  PIN(31, ANT_SEL2, 0, 2, 0x16, 0x50,
152  ANT_SEL2, EXT_FRAME_SYNC, SRCLKENAI1, RES4,
153  RES5, RES6, RES7),
154  PIN(32, URXD0, 0, 25, 0x12, 0x60,
155  URXD0, UTXD0, ADSP_UART_RX, TP_URXD1_AO,
156  RES5, RES6, RES7),
157  PIN(33, UTXD0, 0, 27, 0x12, 0x60,
158  UTXD0, URXD0, ADSP_UART_TX, TP_UTXD1_AO,
159  RES5, RES6, RES7),
160  PIN(34, URXD1, 0, 26, 0x12, 0x60,
161  URXD1, TP_URXD2_AO, SSPM_URXD_AO, ADSP_UART_RX,
162  CONN_UART0_RXD, RES6, RES7),
163  PIN(35, UTXD1, 0, 28, 0x12, 0x60,
164  UTXD1, TP_UTXD2_AO, SSPM_UTXD_AO, ADSP_UART_TX,
165  CONN_UART0_TXD, CONN_WIFI_TXD, RES7),
166  PIN(36, SPI0_CLK, 0, 9, 0x12, 0x60,
167  SPI0_CLK_A, CLKM0, RES3, SCP_SPI0_CK,
168  SPINOR_CK, RES6, dbg_mon_a11),
169  PIN(37, SPI0_CSB, 0, 10, 0x12, 0x60,
170  SPI0_CSB_A, CLKM1, PWM0, SCP_SPI0_CS,
171  SPINOR_CS, RES6, dbg_mon_a12),
172  PIN(38, SPI0_MO, 0, 12, 0x12, 0x60,
173  SPI0_MO_A, CLKM2, PWM1, SCP_SPI0_MO,
174  SPINOR_IO0, RES6, dbg_mon_a13),
175  PIN(39, SPI0_MI, 0, 11, 0x12, 0x60,
176  SPI0_MI_A, CLKM3, PWM2, SCP_SPI0_MI,
177  SPINOR_IO1, RES6, dbg_mon_a14),
178  PIN(40, SPI1_CLK, 0, 13, 0x12, 0x60,
179  SPI1_CLK_A, SCP_SPI1_CK, RES3, UCTS0,
180  SPINOR_IO2, TP_UCTS1_AO, dbg_mon_a15),
181  PIN(41, SPI1_CSB, 0, 14, 0x12, 0x60,
182  SPI1_CSB_A, SCP_SPI1_CS, PWM0, URTS0,
183  SPINOR_IO3, TP_URTS1_AO, dbg_mon_a16),
184  PIN(42, SPI1_MO, 0, 16, 0x12, 0x60,
185  SPI1_MO_A, SCP_SPI1_MO, PWM1, UCTS1,
186  RES5, TP_UCTS2_AO, dbg_mon_a17),
187  PIN(43, SPI1_MI, 0, 15, 0x12, 0x60,
188  SPI1_MI_A, SCP_SPI1_MI, PWM2, URTS1,
189  RES5, TP_URTS2_AO, dbg_mon_a18),
190  PIN(44, SPI2_CK, 0, 28, 0x25, 0x90,
191  SPI2_CLK_A, SCP_SPI0_CK, RES3, RES4,
192  RES5, RES6, dbg_mon_a19),
193  PIN(45, SPI2_CSB, 0, 29, 0x25, 0x90,
194  SPI2_CSB_A, SCP_SPI0_CS, RES3, RES4,
195  RES5, RES6, dbg_mon_a20),
196  PIN(46, SPI2_MO, 0, 31, 0x25, 0x90,
197  SPI2_MO_A, SCP_SPI0_MO, RES3, RES4,
198  RES5, RES6, dbg_mon_a21),
199  PIN(47, SPI2_MI, 0, 30, 0x25, 0x90,
200  SPI2_MI_A, SCP_SPI0_MI, RES3, RES4,
201  RES5, RES6, dbg_mon_a22),
202  PIN(48, SPI3_CLK, 0, 17, 0x12, 0x60,
203  SPI3_CLK, TP_URXD1_AO, TP_URXD2_AO, URXD1,
204  I2S2_MCK, SCP_SPI0_CK, RES7),
205  PIN(49, SPI3_CSB, 0, 18, 0x12, 0x60,
206  SPI3_CSB, TP_UTXD1_AO, TP_UTXD2_AO, UTXD1,
207  I2S2_BCK, SCP_SPI0_CS, RES7),
208  PIN(50, SPI3_MO, 0, 20, 0x12, 0x60,
209  SPI3_MO, RES2, RES3, RES4,
210  I2S2_LRCK, SCP_SPI0_MO, RES7),
211  PIN(51, SPI3_MI, 0, 19, 0x12, 0x60,
212  SPI3_MI, RES2, RES3, RES4,
213  I2S2_DI, SCP_SPI0_MI, RES7),
214  PIN(52, SPI5_CLK, 0, 12, 0x23, 0x80,
215  SPI5_CLK, I2S2_MCK, I2S1_MCK, SCP_SPI1_CK,
216  LVTS_26M, DFD_TCK_XI, dbg_mon_b30),
217  PIN(53, SPI5_CSB, 0, 13, 0x23, 0x80,
218  SPI5_CSB, I2S2_BCK, I2S1_BCK, SCP_SPI1_CS,
219  LVTS_FOUT, DFD_TDI, dbg_mon_b31),
220  PIN(54, SPI5_MO, 0, 15, 0x23, 0x80,
221  SPI5_MO, I2S2_LRCK, I2S1_LRCK, SCP_SPI1_MO,
222  LVTS_SCK, DFD_TDO, dbg_mon_a1),
223  PIN(55, SPI5_MI, 0, 14, 0x23, 0x80,
224  SPI5_MI, I2S2_DI, I2S1_DO, SCP_SPI1_MI,
225  LVTS_SDO, DFD_TMS, dbg_mon_b32),
226  PIN(56, I2S1_DO, 0, 12, 0x25, 0x90,
227  I2S1_DO, I2S3_DO, RES3, RES4,
228  RES5, RES6, dbg_mon_a23),
229  PIN(57, I2S1_BCK, 0, 11, 0x25, 0x90,
230  I2S1_BCK, I2S3_BCK, RES3, RES4,
231  RES5, RES6, dbg_mon_a24),
232  PIN(58, I2S1_LRCK, 0, 13, 0x25, 0x90,
233  I2S1_LRCK, I2S3_LRCK, RES3, RES4,
234  RES5, RES6, dbg_mon_a25),
235  PIN(59, I2S1_MCK, 0, 14, 0x25, 0x90,
236  I2S1_MCK, I2S3_MCK, RES3, RES4,
237  RES5, RES6, dbg_mon_a27),
238  PIN(60, TDM_RX_LRCK, 0, 21, 0x23, 0x80,
239  TDM_RX_LRCK, ANT_SEL3, RES3, RES4,
240  CONN_MCU_DBGACK_N, RES6, RES7),
241  PIN(61, TDM_RX_BCK, 0, 16, 0x23, 0x80,
242  TDM_RX_BCK, ANT_SEL4, RES3, SPINOR_CK,
243  CONN_MCU_DBGI_N, RES6, RES7),
244  PIN(62, TDM_RX_MCLK, 0, 22, 0x23, 0x80,
245  TDM_RX_MCK, ANT_SEL5, RES3, SPINOR_CS,
246  CONN_MCU_TDI, RES6, RES7),
247  PIN(63, TDM_RX_DATA0, 0, 17, 0x23, 0x80,
248  TDM_RX_DATA0, ANT_SEL6, RES3, SPINOR_IO0,
249  CONN_MCU_TRST_B, RES6, RES7),
250  PIN(64, TDM_RX_DATA1, 0, 18, 0x23, 0x80,
251  TDM_RX_DATA1, ANT_SEL7, PWM0, SPINOR_IO1,
252  CONN_MCU_TCK, RES6, RES7),
253  PIN(65, TDM_RX_DATA2, 0, 19, 0x23, 0x80,
254  TDM_RX_DATA2, UCTS0, PWM1, SPINOR_IO2,
255  CONN_MCU_TDO, TP_UCTS1_AO, TP_UCTS2_AO),
256  PIN(66, TDM_RX_DATA3, 0, 20, 0x23, 0x80,
257  TDM_RX_DATA3, URTS0, PWM2, SPINOR_IO3,
258  CONN_MCU_TMS, TP_URTS1_AO, TP_URTS2_AO),
259  PIN(67, MSDC0_DSL, 1, 10, 0x21, 0x70,
260  MSDC0_DSL, RES2, RES3, RES4,
261  RES5, RES6, RES7),
262  PIN(68, MSDC0_CLK, 1, 0, 0x21, 0x70,
263  MSDC0_CLK, RES2, RES3, RES4,
264  RES5, RES6, RES7),
265  PIN(69, MSDC0_CMD, 1, 1, 0x21, 0x70,
266  MSDC0_CMD, RES2, RES3, RES4,
267  RES5, RES6, RES7),
268  PIN(70, MSDC0_RSTB, 1, 11, 0x21, 0x70,
269  MSDC0_RSTB, RES2, RES3, RES4,
270  RES5, RES6, RES7),
271  PIN(71, MSDC0_DAT0, 1, 2, 0x21, 0x70,
272  MSDC0_DAT0, RES2, RES3, RES4,
273  RES5, RES6, RES7),
274  PIN(72, MSDC0_DAT1, 1, 3, 0x21, 0x70,
275  MSDC0_DAT1, RES2, RES3, RES4,
276  RES5, RES6, RES7),
277  PIN(73, MSDC0_DAT2, 1, 4, 0x21, 0x70,
278  MSDC0_DAT2, RES2, RES3, RES4,
279  RES5, RES6, RES7),
280  PIN(74, MSDC0_DAT3, 1, 5, 0x21, 0x70,
281  MSDC0_DAT3, RES2, RES3, RES4,
282  RES5, RES6, RES7),
283  PIN(75, MSDC0_DAT4, 1, 6, 0x21, 0x70,
284  MSDC0_DAT4, RES2, RES3, RES4,
285  RES5, RES6, RES7),
286  PIN(76, MSDC0_DAT5, 1, 7, 0x21, 0x70,
287  MSDC0_DAT5, RES2, RES3, RES4,
288  RES5, RES6, RES7),
289  PIN(77, MSDC0_DAT6, 1, 8, 0x21, 0x70,
290  MSDC0_DAT6, RES2, RES3, RES4,
291  RES5, RES6, RES7),
292  PIN(78, MSDC0_DAT7, 1, 9, 0x21, 0x70,
293  MSDC0_DAT7, RES2, RES3, RES4,
294  RES5, RES6, RES7),
295  PIN(79, KPCOL0, 1, 0, 0x25, 0x80,
296  KPCOL0, RES2, RES3, RES4,
297  RES5, RES6, RES7),
298  PIN(80, KPCOL1, 1, 1, 0x25, 0x80,
299  KPCOL1, GPS_L1_ELNA_EN, PWM0, CLKM0,
300  RES5, RES6, RES7),
301  PIN(81, KPROW0, 1, 2, 0x25, 0x80,
302  KPROW0, RES2, PWM1, CLKM1,
303  RES5, RES6, RES7),
304  PIN(82, KPROW1, 1, 3, 0x25, 0x80,
305  KPROW1, RES2, PWM2, CLKM2,
306  RES5, RES6, RES7),
307  PIN(83, AP_GOOD, 0, 3, 0x16, 0x50,
308  AP_GOOD, GPS_PPS, RES3, EXT_FRAME_SYNC,
309  RES5, RES6, dbg_mon_a28),
310  PIN(84, MSDC1_CLK, 1, 0, 0x23, 0x70,
311  MSDC1_CLK, ADSP_JTAG_TCK, RES3, UDI_TCK,
312  CONN_DSP_JCK, SSPM_JTAG_TCK, DFD_TCK_XI),
313  PIN(85, MSDC1_CMD, 1, 1, 0x23, 0x70,
314  MSDC1_CMD, ADSP_JTAG_TMS, CONN_MCU_AICE_TMSC, UDI_TMS,
315  CONN_DSP_JMS, SSPM_JTAG_TMS, DFD_TMS),
316  PIN(86, MSDC1_DAT0, 1, 2, 0x23, 0x70,
317  MSDC1_DAT0, ADSP_JTAG_TDI, RES3, UDI_TDI,
318  CONN_DSP_JDI, SSPM_JTAG_TDI, DFD_TDI),
319  PIN(87, MSDC1_DAT1, 1, 3, 0x23, 0x70,
320  MSDC1_DAT1, ADSP_JTAG_TDO, RES3, UDI_TDO,
321  CONN_DSP_JDO, SSPM_JTAG_TDO, DFD_TDO),
322  PIN(88, MSDC1_DAT2, 1, 4, 0x23, 0x70,
323  MSDC1_DAT2, ADSP_JTAG_TRSTN, CONN_MCU_AICE_TCKC, UDI_NTRST,
324  CONN_WIFI_TXD, SSPM_JTAG_TRSTN, RES7),
325  PIN(89, MSDC1_DAT3, 1, 5, 0x23, 0x70,
326  MSDC1_DAT3, RES2, RES3, RES4,
327  CONN_DSP_JINTP, RES6, RES7),
328  PIN(90, IDDIG_P0, 0, 2, 0x23, 0x80,
329  IDDIG_P0, RES2, RES3, PGD_HV_HSC_PWR4,
330  GDU_SUM_TROOP2_2, RES6, RES7),
331  PIN(91, USB_DRVVBUS_P0, 0, 23, 0x23, 0x80,
332  USB_DRVVBUS_P0, RES2, RES3, PGD_HV_HSC_PWR5,
333  GDU_TROOPS_DET0, RES6, RES7),
334  PIN(92, VBUS_VALID_P0, 0, 25, 0x23, 0x80,
335  VBUS_VALID_P0, RES2, RES3, PGD_DA_EFUSE_RDY,
336  GDU_TROOPS_DET1, RES6, RES7),
337  PIN(93, IDDIG_P1, 0, 3, 0x23, 0x80,
338  IDDIG_P1, PWM0, CLKM0, PGD_DA_EFUSE_RDY_PRE,
339  GDU_TROOPS_DET2, RES6, RES7),
340  PIN(94, USB_DRVVBUS_P1, 0, 24, 0x23, 0x80,
341  USB_DRVVBUS_P1, PWM1, CLKM1, PGD_DA_PWRGD_RESET,
342  RES5, RES6, RES7),
343  PIN(95, VBUS_VALID_P1, 0, 26, 0x23, 0x80,
344  VBUS_VALID_P1, PWM2, CLKM2, PGD_DA_PWRGD_ENB,
345  RES5, RES6, RES7),
346  PIN(96, DSI_TE, 0, 1, 0x12, 0x60,
347  DSI_TE, RES2, RES3, RES4,
348  RES5, RES6, dbg_mon_a29),
349  PIN(97, DISP_PWM, 0, 0, 0x12, 0x60,
350  DISP_PWM, RES2, RES3, RES4,
351  RES5, RES6, dbg_mon_a30),
352  PIN(98, LCM_RST, 0, 2, 0x12, 0x60,
353  LCM_RST, RES2, RES3, RES4,
354  RES5, RES6, RES7),
355  PIN(99, DPI_PCLK, 0, 14, 0x24, 0x60,
356  DPI_PCLK, GPS_L1_ELNA_EN, SSPM_JTAG_TCK, RES4,
357  ANT_SEL0, TP_GPIO0_AO, PGD_LV_LSC_PWR0),
358  PIN(100, DPI_VSYNC, 0, 15, 0x24, 0x60,
359  DPI_VSYNC, KPCOL2, SSPM_JTAG_TMS, RES4,
360  ANT_SEL1, TP_GPIO1_AO, PGD_LV_LSC_PWR1),
361  PIN(101, DPI_HSYNC, 0, 13, 0x24, 0x60,
362  DPI_HSYNC, KPROW2, SSPM_JTAG_TDI, RES4,
363  ANT_SEL2, TP_GPIO2_AO, PGD_LV_LSC_PWR2),
364  PIN(102, DPI_DE, 0, 12, 0x24, 0x60,
365  DPI_DE, RES2, SSPM_JTAG_TDO, RES4,
366  ANT_SEL3, TP_GPIO3_AO, PGD_LV_LSC_PWR3),
367  PIN(103, DPI_DATA0, 0, 0, 0x24, 0x60,
368  DPI_DATA0, RES2, SSPM_JTAG_TRSTN, CLKM0,
369  ANT_SEL4, TP_GPIO4_AO, PGD_LV_LSC_PWR4),
370  PIN(104, DPI_DATA1, 0, 1, 0x24, 0x60,
371  DPI_DATA1, GPS_PPS, UCTS2, CLKM1,
372  ANT_SEL5, TP_GPIO5_AO, PGD_LV_LSC_PWR5),
373  PIN(105, DPI_DATA2, 0, 4, 0x24, 0x60,
374  DPI_DATA2, CONN_TCXOENA_REQ, URTS2, CLKM2,
375  ANT_SEL6, TP_GPIO6_AO, PGD_LV_HSC_PWR0),
376  PIN(106, DPI_DATA3, 0, 5, 0x24, 0x60,
377  DPI_DATA3, TP_UTXD1_AO, UTXD2, PWM0,
378  ANT_SEL7, TP_GPIO7_AO, PGD_LV_HSC_PWR1),
379  PIN(107, DPI_DATA4, 0, 6, 0x24, 0x60,
380  DPI_DATA4, TP_URXD1_AO, URXD2, PWM1,
381  RES5, GDU_SUM_TROOP0_0, PGD_LV_HSC_PWR2),
382  PIN(108, DPI_DATA5, 0, 7, 0x24, 0x60,
383  DPI_DATA5, TP_UCTS1_AO, UCTS0, PWM2,
384  RES5, GDU_SUM_TROOP0_1, PGD_LV_HSC_PWR3),
385  PIN(109, DPI_DATA6, 0, 8, 0x24, 0x60,
386  DPI_DATA6, TP_URTS1_AO, URTS0, I2S0_DI,
387  I2S2_DI, GDU_SUM_TROOP0_2, PGD_LV_HSC_PWR4),
388  PIN(110, DPI_DATA7, 0, 9, 0x24, 0x60,
389  DPI_DATA7, TP_UCTS2_AO, UCTS1, I2S3_BCK,
390  I2S1_BCK, GDU_SUM_TROOP1_0, PGD_LV_HSC_PWR5),
391  PIN(111, DPI_DATA8, 0, 10, 0x24, 0x60,
392  DPI_DATA8, TP_URTS2_AO, URTS1, I2S3_MCK,
393  I2S1_MCK, GDU_SUM_TROOP1_1, PGD_HV_HSC_PWR0),
394  PIN(112, DPI_DATA9, 0, 11, 0x24, 0x60,
395  DPI_DATA9, TP_URXD2_AO, URXD1, I2S3_LRCK,
396  I2S1_LRCK, GDU_SUM_TROOP1_2, PGD_HV_HSC_PWR1),
397  PIN(113, DPI_DATA10, 0, 2, 0x24, 0x60,
398  DPI_DATA10, TP_UTXD2_AO, UTXD1, I2S3_DO,
399  I2S1_DO, GDU_SUM_TROOP2_0, PGD_HV_HSC_PWR2),
400  PIN(114, DPI_DATA11, 0, 3, 0x24, 0x60,
401  DPI_DATA11, RES2, RES3, RES4,
402  RES5, GDU_SUM_TROOP2_1, PGD_HV_HSC_PWR3),
403  PIN(115, PCM_CLK, 0, 4, 0x23, 0x80,
404  PCM_CLK, I2S0_BCK, I2S2_BCK, RES4,
405  RES5, RES6, RES7),
406  PIN(116, PCM_SYNC, 0, 7, 0x23, 0x80,
407  PCM_SYNC, I2S0_LRCK, I2S2_LRCK, RES4,
408  RES5, RES6, RES7),
409  PIN(117, PCM_DI, 0, 5, 0x23, 0x80,
410  PCM_DI, I2S0_DI, I2S2_DI, RES4,
411  RES5, RES6, RES7),
412  PIN(118, PCM_DO, 0, 6, 0x23, 0x80,
413  PCM_DO, I2S0_MCK, I2S2_MCK, I2S3_DO,
414  I2S1_DO, RES6, RES7),
415  PIN(119, JTMS_SEL1, 0, 22, 0x25, 0x90,
416  JTMS_SEL1, UDI_TMS, DFD_TMS, SPM_JTAG_TMS,
417  SCP_JTAG_TMS, ADSP_JTAG_TMS, RES7),
418  PIN(120, JTCK_SEL1, 0, 19, 0x25, 0x90,
419  JTCK_SEL1, UDI_TCK, DFD_TCK_XI, SPM_JTAG_TCK,
420  SCP_JTAG_TCK, ADSP_JTAG_TCK, RES7),
421  PIN(121, JTDI_SEL1, 0, 20, 0x25, 0x90,
422  JTDI_SEL1, UDI_TDI, DFD_TDI, SPM_JTAG_TDI,
423  SCP_JTAG_TDI, ADSP_JTAG_TDI, RES7),
424  PIN(122, JTDO_SEL1, 0, 21, 0x25, 0x90,
425  JTDO_SEL1, UDI_TDO, DFD_TDO, SPM_JTAG_TDO,
426  SCP_JTAG_TDO, ADSP_JTAG_TDO, RES7),
427  PIN(123, JTRSTN_SEL1, 0, 23, 0x25, 0x90,
428  JTRSTN_SEL1, UDI_NTRST, RES3, SPM_JTAG_TRSTN,
429  SCP_JTAG_TRSTN, ADSP_JTAG_TRSTN, RES7),
430  PIN(124, CAM_CLK0, 0, 0, 0x25, 0x90,
431  CMMCLK0, CLKM0, PWM0, RES4,
432  RES5, RES6, RES7),
433  PIN(125, CAM_CLK1, 0, 1, 0x25, 0x90,
434  CMMCLK1, CLKM1, PWM1, RES4,
435  RES5, RES6, dbg_mon_b0),
436  PIN(126, CAM_CLK2, 0, 2, 0x25, 0x90,
437  CMMCLK2, CLKM2, PWM2, RES4,
438  RES5, RES6, dbg_mon_b1),
439  PIN(127, SCL0, 0, 8, 0x23, 0x80,
440  SCL0, RES2, RES3, SCP_SCL0,
441  SCP_SCL1, RES6, RES7),
442  PIN(128, SDA0, 0, 10, 0x23, 0x80,
443  SDA0, RES2, RES3, SCP_SDA0,
444  SCP_SDA1, RES6, RES7),
445  PIN(129, SCL1, 0, 24, 0x25, 0x90,
446  SCL1, RES2, RES3, SCP_SCL0,
447  SCP_SCL1, RES6, dbg_mon_b4),
448  PIN(130, SDA1, 0, 26, 0x25, 0x90,
449  SDA1, RES2, RES3, SCP_SDA0,
450  SCP_SDA1, RES6, dbg_mon_b5),
451  PIN(131, SCL2, 0, 25, 0x25, 0x90,
452  SCL2, SSPM_UTXD_AO, CONN_UART0_TXD, SCP_SCL0,
453  SCP_SCL1, RES6, dbg_mon_b6),
454  PIN(132, SDA2, 0, 27, 0x25, 0x90,
455  SDA2, SSPM_URXD_AO, CONN_UART0_RXD, SCP_SDA0,
456  SCP_SDA1, RES6, dbg_mon_b7),
457  PIN(133, SCL3, 0, 9, 0x21, 0x80,
458  SCL3, RES2, RES3, SCP_SCL0,
459  SCP_SCL1, RES6, dbg_mon_b8),
460  PIN(134, SDA3, 0, 12, 0x21, 0x80,
461  SDA3, RES2, GPS_PPS, SCP_SDA0,
462  SCP_SDA1, RES6, dbg_mon_b9),
463  PIN(135, SCL4, 0, 21, 0x16, 0x50,
464  SCL4, TP_UTXD1_AO, UTXD1, SCP_SCL0,
465  SCP_SCL1, RES6, dbg_mon_b10),
466  PIN(136, SDA4, 0, 24, 0x16, 0x50,
467  SDA4, TP_URXD1_AO, URXD1, SCP_SDA0,
468  SCP_SDA1, RES6, dbg_mon_b11),
469  PIN(137, SCL5, 0, 10, 0x21, 0x80,
470  SCL5, UTXD2, UCTS1, SCP_SCL0,
471  SCP_SCL1, RES6, RES7),
472  PIN(138, SDA5, 0, 13, 0x21, 0x80,
473  SDA5, URXD2, URTS1, SCP_SDA0,
474  SCP_SDA1, RES6, RES7),
475  PIN(139, SCL6, 0, 7, 0x12, 0x60,
476  SCL6, UTXD1, TP_UTXD1_AO, SCP_SCL0,
477  SCP_SCL1, RES6, dbg_mon_b12),
478  PIN(140, SDA6, 0, 8, 0x12, 0x60,
479  SDA6, URXD1, TP_URXD1_AO, SCP_SDA0,
480  SCP_SDA1, RES6, dbg_mon_b13),
481  PIN(141, SCL7, 0, 9, 0x23, 0x80,
482  SCL7, URTS0, TP_URTS1_AO, SCP_SCL0,
483  SCP_SCL1, UDI_TCK, dbg_mon_b14),
484  PIN(142, SDA7, 0, 11, 0x23, 0x80,
485  SDA7, UCTS0, TP_UCTS1_AO, SCP_SDA0,
486  SCP_SDA1, RES6, RES7),
487  PIN(143, SCL8, 0, 22, 0x16, 0x50,
488  SCL8, RES2, RES3, SCP_SCL0,
489  SCP_SCL1, RES6, dbg_mon_b16),
490  PIN(144, SDA8, 0, 25, 0x16, 0x50,
491  SDA8, RES2, RES3, SCP_SDA0,
492  SCP_SDA1, RES6, dbg_mon_b17),
493  PIN(145, SCL9, 0, 23, 0x16, 0x50,
494  SCL9, CMVREF1, GPS_PPS, SCP_SCL0,
495  SCP_SCL1, RES6, dbg_mon_b18),
496  PIN(146, SDA9, 0, 26, 0x16, 0x50,
497  SDA9, CMVREF0, RES3, SCP_SDA0,
498  SCP_SDA1, RES6, dbg_mon_b19),
499  PIN(147, PERIPHERAL_EN0, 0, 23, 0x24, 0x60,
500  CMFLASH0, LVTS_SDI, DPI_DATA12, TP_GPIO0_AO,
501  ANT_SEL3, DFD_TCK_XI, dbg_mon_b20),
502  PIN(148, PERIPHERAL_EN1, 0, 24, 0x24, 0x60,
503  CMFLASH1, LVTS_SCF, DPI_DATA13, TP_GPIO1_AO,
504  ANT_SEL4, DFD_TMS, dbg_mon_b21),
505  PIN(149, PERIPHERAL_EN2, 0, 25, 0x24, 0x60,
506  CMFLASH2, CLKM0, DPI_DATA14, TP_GPIO2_AO,
507  ANT_SEL5, DFD_TDI, dbg_mon_b22),
508  PIN(150, PERIPHERAL_EN3, 0, 26, 0x24, 0x60,
509  RES1, CLKM1, DPI_DATA15, TP_GPIO3_AO,
510  ANT_SEL6, DFD_TDO, dbg_mon_b23),
511  PIN(151, PERIPHERAL_EN4, 0, 27, 0x24, 0x60,
512  GPS_L1_ELNA_EN, CLKM2, DPI_DATA16, TP_GPIO4_AO,
513  ANT_SEL7, UDI_TMS, dbg_mon_b24),
514  PIN(152, PERIPHERAL_EN5, 0, 28, 0x24, 0x60,
515  RES1, CLKM3, DPI_DATA17, TP_GPIO5_AO,
516  RES5, RES6, RES7),
517  PIN(153, PERIPHERAL_EN6, 0, 29, 0x24, 0x60,
518  CONN_TCXOENA_REQ, RES2, DPI_DATA18, TP_GPIO6_AO,
519  RES5, UDI_TDI, dbg_mon_b26),
520  PIN(154, PERIPHERAL_EN7, 0, 30, 0x24, 0x60,
521  PWM0, CMVREF2, DPI_DATA19, TP_GPIO7_AO,
522  RES5, UDI_TDO, dbg_mon_b27),
523  PIN(155, PERIPHERAL_EN8, 0, 31, 0x24, 0x60,
524  PWM1, CMVREF1, DPI_DATA20, RES4,
525  RES5, UDI_NTRST, dbg_mon_b28),
526  PIN(156, PERIPHERAL_EN9, 0, 0, 0x24, 0x70,
527  PWM2, CMVREF0, DPI_DATA21, RES4,
528  RES5, RES6, RES7),
529  PIN(157, PWRAP_SPI0_CSN, 0, 4, 0x12, 0x60,
530  PWRAP_SPI0_CSN, RES2, RES3, RES4,
531  RES5, RES6, RES7),
532  PIN(158, PWRAP_SPI0_CK, 0, 3, 0x12, 0x60,
533  PWRAP_SPI0_CK, RES2, RES3, RES4,
534  RES5, RES6, RES7),
535  PIN(159, PWRAP_SPI0_MO, 0, 6, 0x12, 0x60,
536  PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4,
537  RES5, RES6, RES7),
538  PIN(160, PWRAP_SPI0_MI, 0, 5, 0x12, 0x60,
539  PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4,
540  RES5, RES6, RES7),
541  PIN(161, SRCLKENA0, 0, 23, 0x12, 0x60,
542  SRCLKENA0, RES2, RES3, RES4,
543  RES5, RES6, RES7),
544  PIN(162, SRCLKENA1, 0, 24, 0x12, 0x60,
545  SRCLKENA1, RES2, RES3, RES4,
546  RES5, RES6, dbg_mon_a31),
547  PIN(163, SCP_VREQ_VAO, 0, 11, 0x21, 0x80,
548  SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4,
549  RES5, RES6, RES7),
550  PIN(164, RTC32K_CK, 0, 8, 0x21, 0x80,
551  RTC32K_CK, RES2, RES3, RES4,
552  RES5, RES6, RES7),
553  PIN(165, WATCHDOG, 0, 16, 0x21, 0x80,
554  WATCHDOG, RES2, RES3, RES4,
555  RES5, RES6, RES7),
556  PIN(166, AUD_CLK_MOSI, 0, 1, 0x21, 0x80,
557  AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4,
558  RES5, RES6, RES7),
559  PIN(167, AUD_SYNC_MOSI, 0, 7, 0x21, 0x80,
560  AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4,
561  RES5, RES6, RES7),
562  PIN(168, AUD_DAT_MOSI0, 0, 4, 0x21, 0x80,
563  AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4,
564  RES5, RES6, RES7),
565  PIN(169, AUD_DAT_MOSI1, 0, 5, 0x21, 0x80,
566  AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4,
567  RES5, RES6, RES7),
568  PIN(170, AUD_CLK_MISO, 0, 0, 0x21, 0x80,
569  AUD_CLK_MISO, AUD_CLK_MOSI, I2S2_MCK, RES4,
570  RES5, RES6, RES7),
571  PIN(171, AUD_SYNC_MISO, 0, 6, 0x21, 0x80,
572  AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S2_BCK, RES4,
573  RES5, RES6, RES7),
574  PIN(172, AUD_DAT_MISO0, 0, 2, 0x21, 0x80,
575  AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S2_LRCK, VOW_DAT_MISO,
576  RES5, RES6, RES7),
577  PIN(173, AUD_DAT_MISO1, 0, 3, 0x21, 0x80,
578  AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S2_DI, VOW_CLK_MISO,
579  RES5, RES6, RES7),
580  PIN(174, CONN_TOP_CLK, 0, 7, 0x16, 0x50,
581  CONN_TOP_CLK, AUXIF_CLK, DFD_TCK_XI, RES4,
582  RES5, RES6, dbg_mon_b3),
583  PIN(175, CONN_TOP_DATA, 0, 8, 0x16, 0x50,
584  CONN_TOP_DATA, AUXIF_ST, DFD_TMS, RES4,
585  RES5, RES6, dbg_mon_b15),
586  PIN(176, CONN_BT_CLK, 0, 4, 0x16, 0x50,
587  CONN_BT_CLK, RES2, DFD_TDI, RES4,
588  RES5, RES6, dbg_mon_b2),
589  PIN(177, CONN_BT_DATA, 0, 5, 0x16, 0x50,
590  CONN_BT_DATA, RES2, DFD_TDO, RES4,
591  RES5, RES6, RES7),
592  PIN(178, CONN_HRST_B, 0, 6, 0x16, 0x50,
593  CONN_HRST_B, RES2, UDI_TMS, RES4,
594  RES5, RES6, dbg_mon_b25),
595  PIN(179, CONN_WB_PTA, 0, 9, 0x16, 0x50,
596  CONN_WB_PTA, RES2, UDI_TCK, RES4,
597  RES5, RES6, dbg_mon_b29),
598  PIN(180, CONN_WF_CTRL0, 0, 10, 0x16, 0x50,
599  CONN_WF_CTRL0, RES2, UDI_TDI, RES4,
600  RES5, RES6, RES7),
601  PIN(181, CONN_WF_CTRL1, 0, 11, 0x16, 0x50,
602  CONN_WF_CTRL1, RES2, UDI_TDO, RES4,
603  RES5, RES6, RES7),
604  PIN(182, CONN_WF_CTRL2, 0, 12, 0x16, 0x50,
605  CONN_WF_CTRL2, RES2, UDI_NTRST, RES4,
606  RES5, RES6, RES7),
607  PIN(183, SPMI_SCL, 0, 21, 0x12, 0x60,
608  SPMI_SCL, RES2, RES3, RES4,
609  RES5, RES6, RES7),
610  PIN(184, SPMI_SDA, 0, 22, 0x12, 0x60,
611  SPMI_SDA, RES2, RES3, RES4,
612  RES5, RES6, RES7),
613 };
614 
615 struct val_regs {
616  uint32_t val;
617  uint32_t set;
618  uint32_t rst;
619  uint32_t align;
620 };
621 
622 struct gpio_regs {
623  struct val_regs dir[7];
624  uint8_t rsv00[144];
625  struct val_regs dout[7];
626  uint8_t rsv01[144];
627  struct val_regs din[7];
628  uint8_t rsv02[144];
629  struct val_regs mode[28];
630  uint8_t rsv03[560];
632 };
633 
634 check_member(gpio_regs, mode[27].val, 0x4b0);
635 check_member(gpio_regs, dram_pinmux_trapping, 0x6f0);
636 
637 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
638 
639 #endif
#define SPI0_CLK
#define GPIO_BASE
Definition: lpc.h:21
check_member(gpio_regs, msdc2_ctrl5, 0xcb0)
@ MAX_GPIO_MODE_PER_REG
Definition: gpio.h:11
@ GPIO_MODE_BITS
Definition: gpio.h:12
@ MAX_GPIO_REG_BITS
Definition: gpio.h:10
gpio_drv
Definition: gpio.h:23
@ GPIO_DRV_2_MA
Definition: gpio.h:24
@ GPIO_DRV_14_MA
Definition: gpio.h:30
@ GPIO_DRV_10_MA
Definition: gpio.h:28
@ GPIO_DRV_4_MA
Definition: gpio.h:25
@ GPIO_DRV_12_MA
Definition: gpio.h:29
@ GPIO_DRV_16_MA
Definition: gpio.h:31
@ GPIO_DRV_6_MA
Definition: gpio.h:26
@ GPIO_DRV_8_MA
Definition: gpio.h:27
static struct gpio_regs *const mtk_gpio
Definition: gpio.h:637
#define PIN(id, name, flag, bit, base, offset, func1, func2, func3, func4, func5, func6, func7)
Definition: gpio.h:34
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8
struct val_regs din[9]
Definition: gpio.h:322
uint8_t rsv00[112]
Definition: gpio.h:314
struct val_regs mode[27]
Definition: gpio.h:324
uint8_t rsv03[256]
Definition: gpio.h:319
uint8_t rsv02[112]
Definition: gpio.h:318
struct val_regs dout[9]
Definition: gpio.h:320
uint8_t rsv01[112]
Definition: gpio.h:316
uint32_t dram_pinmux_trapping
Definition: gpio.h:631
struct val_regs dir[9]
Definition: gpio.h:313
Definition: gpio.h:305
uint32_t align
Definition: gpio.h:309
uint32_t set
Definition: gpio.h:307
uint32_t val
Definition: gpio.h:306
uint32_t rst
Definition: gpio.h:308
u8 val
Definition: sys.c:300