5 #ifndef _SIFIVE_UX00DDR_H
6 #define _SIFIVE_UX00DDR_H
13 #define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
15 #define DRAM_CLASS_OFFSET 8
16 #define DRAM_CLASS_DDR4 0xA
17 #define OPTIMAL_RMODW_EN_OFFSET 0
18 #define DISABLE_RD_INTERLEAVE_OFFSET 16
19 #define OUT_OF_RANGE_OFFSET 1
20 #define MULTIPLE_OUT_OF_RANGE_OFFSET 2
21 #define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
22 #define MC_INIT_COMPLETE_OFFSET 8
23 #define LEVELING_OPERATION_COMPLETED_OFFSET 22
24 #define DFI_PHY_WRLELV_MODE_OFFSET 24
25 #define DFI_PHY_RDLVL_MODE_OFFSET 24
26 #define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
27 #define VREF_EN_OFFSET 24
28 #define PORT_ADDR_PROTECTION_EN_OFFSET 0
29 #define AXI0_ADDRESS_RANGE_ENABLE 8
30 #define AXI0_RANGE_PROT_BITS_0_OFFSET 24
31 #define RDLVL_EN_OFFSET 16
32 #define RDLVL_GATE_EN_OFFSET 24
33 #define WRLVL_EN_OFFSET 0
35 #define PHY_RX_CAL_DQ0_0_OFFSET 0
36 #define PHY_RX_CAL_DQ1_0_OFFSET 16
40 for (i=1152;i<=1214;i++) {
42 ddrphyreg[i] = physet;
44 for (i=0;i<=1151;i++) {
46 ddrphyreg[i] = physet;
55 for (i=0;i<=264;i++) {
57 ddrctlreg[i] = ctlset;
63 static inline void ux00ddr_start(
size_t ahbregaddr,
size_t filteraddr,
size_t ddrend) {
67 _REG32(0<<2, ahbregaddr) = regdata;
73 filterreg[0] = 0x0f00000000000000UL | (ddrend >> 2);
103 _REG32(209<<2, ahbregaddr) = 0x0;
104 size_t end_addr_16Kblocks = ((end_addr >> 14) & 0x7FFFFF)-1;
106 _REG32(212<<2, ahbregaddr) = 0x0;
107 _REG32(214<<2, ahbregaddr) = 0x0;
108 _REG32(216<<2, ahbregaddr) = 0x0;
110 _REG32(225<<2, ahbregaddr) = 0xFFFFFFFF;
149 size_t ddrphyreg = ahbregaddr + 0x2000;
156 for (
uint32_t slice = 0; slice < 8; slice++) {
158 for (
uint32_t reg = 0 ; reg < 4; reg++) {
160 for (
uint32_t bit = 0; bit < 2; bit++) {
169 uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
170 uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset+6)) & 0x3F;
172 uint8_t failc0 = ((down == 0) && (up == 0x3F));
173 uint8_t failc1 = ((up == 0) && (down == 0x3F));
176 if (failc0 || failc1) {
181 slicelsc += (dq % 10);
182 slicemsc += (dq / 10);
unsigned long long uint64_t
#define AXI0_RANGE_PROT_BITS_0_OFFSET
#define PHY_RX_CAL_DQ0_0_OFFSET
#define PHY_RX_CAL_DQ1_0_OFFSET
#define DFI_PHY_RDLVL_GATE_MODE_OFFSET
#define LEVELING_OPERATION_COMPLETED_OFFSET
#define PORT_COMMAND_CHANNEL_ERROR_OFFSET
#define DRAM_CLASS_OFFSET
static void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr)
static void ux00ddr_mask_leveling_completed_interrupt(size_t ahbregaddr)
static void phy_reset(volatile uint32_t *ddrphyreg, const uint32_t *physettings)
static void ux00ddr_enablevreftraining(size_t ahbregaddr)
static void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr)
#define MULTIPLE_OUT_OF_RANGE_OFFSET
#define OUT_OF_RANGE_OFFSET
#define PORT_ADDR_PROTECTION_EN_OFFSET
static void ux00ddr_start(size_t ahbregaddr, size_t filteraddr, size_t ddrend)
static void ux00ddr_disableaxireadinterleave(size_t ahbregaddr)
#define MC_INIT_COMPLETE_OFFSET
static void ux00ddr_enablereadlevelinggate(size_t ahbregaddr)
static void ux00ddr_setuprangeprotection(size_t ahbregaddr, size_t end_addr)
static void ux00ddr_disableoptimalrmodw(size_t ahbregaddr)
static void ux00ddr_enablewriteleveling(size_t ahbregaddr)
#define DISABLE_RD_INTERLEAVE_OFFSET
static void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr)
static void ux00ddr_enablereadleveling(size_t ahbregaddr)
#define RDLVL_GATE_EN_OFFSET
#define OPTIMAL_RMODW_EN_OFFSET
#define AXI0_ADDRESS_RANGE_ENABLE
static uint64_t ux00ddr_phy_fixup(size_t ahbregaddr)
static uint32_t ux00ddr_getdramclass(size_t ahbregaddr)
#define DFI_PHY_RDLVL_MODE_OFFSET
static void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings)
#define DFI_PHY_WRLELV_MODE_OFFSET