coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
memory.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <baseboard/variants.h>
4 #include <console/console.h>
5 #include <soc/romstage.h>
6 
7 #include "board_id.h"
8 
9 static const struct mb_cfg ddr4_mem_config = {
10  .type = MEM_TYPE_DDR4,
11 
12  .rcomp = {
13  /* Baseboard uses only 100ohm Rcomp resistor */
14  .resistor = 100,
15 
16  /* Baseboard Rcomp target values */
17  .targets = { 50, 20, 25, 25, 25 },
18  },
19 
20  .ect = true, /* Early Command Training */
21 
22  .UserBd = BOARD_TYPE_MOBILE,
23 
24  .LpDdrDqDqsReTraining = 1,
25 
26  .ddr_config = {
27  .dq_pins_interleaved = false,
28  },
29 };
30 
31 static const struct mb_cfg lpddr4_mem_config = {
32  .type = MEM_TYPE_LP4X,
33 
34  /* DQ byte map */
35  .lpx_dq_map = {
36  .ddr0 = {
37  .dq0 = { 0, 2, 3, 1, 6, 7, 5, 4, },
38  .dq1 = { 10, 8, 11, 9, 14, 12, 13, 15, },
39  },
40  .ddr1 = {
41  .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9, },
42  .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4, },
43  },
44  .ddr2 = {
45  .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, },
46  .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11, },
47  },
48  .ddr3 = {
49  .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5, },
50  .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10, },
51  },
52  .ddr4 = {
53  .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5, },
54  .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15, },
55  },
56  .ddr5 = {
57  .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11, },
58  .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1, },
59  },
60  .ddr6 = {
61  .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8, },
62  .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2, },
63  },
64  .ddr7 = {
65  .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5, },
66  .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15, },
67  },
68  },
69 
70  /* DQS CPU<>DRAM map */
71  .lpx_dqs_map = {
72  .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
73  .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
74  .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
75  .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
76  .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
77  .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
78  .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
79  .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
80  },
81 
82  .LpDdrDqDqsReTraining = 1,
83 
84  .ect = true, /* Early Command Training */
85 
86  .UserBd = BOARD_TYPE_MOBILE,
87 };
88 
89 static const struct mb_cfg lp5_mem_config = {
90  .type = MEM_TYPE_LP5X,
91 
92  /* DQ byte map */
93  .lpx_dq_map = {
94  .ddr0 = {
95  .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
96  .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, },
97  },
98  .ddr1 = {
99  .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, },
100  .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, },
101  },
102  .ddr2 = {
103  .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, },
104  .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, },
105  },
106  .ddr3 = {
107  .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, },
108  .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, },
109  },
110  .ddr4 = {
111  .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, },
112  .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, },
113  },
114  .ddr5 = {
115  .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, },
116  .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, },
117  },
118  .ddr6 = {
119  .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, },
120  .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, },
121  },
122  .ddr7 = {
123  .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
124  .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, },
125  },
126  },
127 
128  /* DQS CPU<>DRAM map */
129  .lpx_dqs_map = {
130  .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
131  .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
132  .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
133  .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
134  .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
135  .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
136  .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
137  .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
138  },
139 
140  .ect = false, /* Early Command Training */
141 
142  .LpDdrDqDqsReTraining = 1,
143 
144  .UserBd = BOARD_TYPE_MOBILE,
145 
146  .lp5x_config = {
147  .ccc_config = 0xff,
148  },
149 };
150 
151 static const struct mb_cfg ddr5_mem_config = {
152  .type = MEM_TYPE_DDR5,
153 
154  .rcomp = {
155  /* Baseboard uses only 100ohm Rcomp resistor */
156  .resistor = 100,
157 
158  /* Baseboard Rcomp target values */
159  .targets = { 50, 30, 30, 30, 27 },
160  },
161 
162  .ect = true, /* Early Command Training */
163 
164  .UserBd = BOARD_TYPE_MOBILE,
165 
166  .LpDdrDqDqsReTraining = 1,
167 
168  .ddr_config = {
169  .dq_pins_interleaved = false,
170  }
171 };
172 
173 static const struct mb_cfg adlm_lp4_mem_config = {
174  .type = MEM_TYPE_LP4X,
175 
176  /* DQ byte map */
177  .lpx_dq_map = {
178  .ddr0 = {
179  .dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
180  .dq1 = { 3, 2, 7, 6, 0, 1, 5, 4, }, /* DDR0_DQ1[7:0] */
181  },
182  .ddr1 = {
183  .dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, }, /* DDR1_DQ0[7:0] */
184  .dq1 = { 0, 1, 7, 6, 2, 5, 4, 3, }, /* DDR1_DQ1[7:0] */
185  },
186  .ddr2 = {
187  .dq0 = { 6, 7, 3, 2, 0, 4, 1, 5, }, /* DDR2_DQ0[7:0] */
188  .dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
189  },
190  .ddr3 = {
191  .dq0 = { 2, 6, 7, 3, 1, 5, 0, 4, }, /* DDR3_DQ0[7:0] */
192  .dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
193  },
194  .ddr4 = {
195  .dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
196  .dq1 = { 1, 0, 5, 4, 6, 2, 3, 7, }, /* DDR4_DQ1[7:0] */
197  },
198  .ddr5 = {
199  .dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
200  .dq1 = { 0, 7, 2, 6, 3, 1, 4, 5, }, /* DDR5_DQ1[7:0] */
201  },
202  .ddr6 = {
203  .dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
204  .dq1 = { 4, 0, 5, 6, 3, 2, 1, 7, }, /* DDR6_DQ1[7:0] */
205  },
206  .ddr7 = {
207  .dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
208  .dq1 = { 7, 1, 2, 3, 6, 0, 5, 4, }, /* DDR7_DQ1[7:0] */
209  },
210  },
211 
212  /* DQS CPU<>DRAM map */
213  .lpx_dqs_map = {
214  .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
215  .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
216  .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
217  .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
218  .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
219  .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
220  .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
221  .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
222  },
223 
224  .ect = true, /* Early Command Training */
225 
226  .CmdMirror = 0xCC,
227 
228  .LpDdrDqDqsReTraining = 1,
229 
230  .UserBd = BOARD_TYPE_ULT_ULX_T4,
231 };
232 
233 static const struct mb_cfg adlm_lp5_mem_config = {
234  .type = MEM_TYPE_LP5X,
235 
236  /* DQ byte map */
237  .lpx_dq_map = {
238  .ddr0 = {
239  .dq0 = { 4, 5, 7, 6, 3, 2, 1, 0, },
240  .dq1 = { 12, 10, 8, 15, 11, 9, 14, 13, },
241  },
242  .ddr1 = {
243  .dq0 = { 1, 0, 2, 3, 7, 4, 5, 6, },
244  .dq1 = { 14, 15, 10, 11, 13, 12, 8, 9, },
245  },
246  .ddr2 = {
247  .dq0 = { 7, 4, 2, 0, 3, 1, 6, 5, },
248  .dq1 = { 14, 13, 15, 12, 8, 9, 10, 11, },
249  },
250  .ddr3 = {
251  .dq0 = { 3, 2, 0, 1, 7, 5, 6, 4, },
252  .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, },
253  },
254  .ddr4 = {
255  .dq0 = { 2, 3, 0, 1, 6, 4, 7, 5, },
256  .dq1 = { 14, 9, 11, 13, 12, 8, 15, 10, },
257  },
258  .ddr5 = {
259  .dq0 = { 4, 7, 3, 1, 5, 2, 6, 0, },
260  .dq1 = { 14, 8, 11, 9, 12, 15, 10, 13, },
261  },
262  .ddr6 = {
263  .dq0 = { 10, 11, 13, 9, 15, 12, 8, 14, },
264  .dq1 = { 2, 4, 7, 0, 6, 3, 5, 1, },
265  },
266  .ddr7 = {
267  .dq0 = { 13, 15, 11, 14, 10, 12, 8, 9, },
268  .dq1 = { 6, 5, 4, 7, 3, 1, 2, 0, },
269  },
270  },
271 
272  /* DQS CPU<>DRAM map */
273  .lpx_dqs_map = {
274  .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
275  .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
276  .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
277  .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
278  .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
279  .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
280  .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
281  .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
282  },
283 
284  .ect = false, /* Early Command Training */
285 
286  .UserBd = BOARD_TYPE_ULT_ULX_T4,
287 
288  .lp5x_config = {
289  .ccc_config = 0xff,
290  },
291 };
292 
293 static const struct mb_cfg adln_lp5_mem_config = {
294  .type = MEM_TYPE_LP5X,
295 
296  /* DQ byte map */
297  .lpx_dq_map = {
298  .ddr0 = {
299  .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
300  .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
301  },
302  .ddr1 = {
303  .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
304  .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
305  },
306  .ddr2 = {
307  .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
308  .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
309  },
310  .ddr3 = {
311  .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
312  .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
313  },
314  .ddr4 = {
315  .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
316  .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
317  },
318  .ddr5 = {
319  .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
320  .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
321  },
322  .ddr6 = {
323  .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
324  .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
325  },
326  .ddr7 = {
327  .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
328  .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
329  },
330  },
331 
332  /* DQS CPU<>DRAM map */
333  .lpx_dqs_map = {
334  .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
335  .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
336  .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
337  .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
338  .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
339  .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
340  .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
341  .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
342  },
343 
344  .ect = true, /* Early Command Training */
345 
346  .UserBd = BOARD_TYPE_ULT_ULX,
347 
348  .LpDdrDqDqsReTraining = 1,
349 
350  .lp5x_config = {
351  .ccc_config = 0xff,
352  },
353 };
354 
355 const struct mb_cfg *variant_memory_params(void)
356 {
357  int board_id = get_board_id();
358 
359  switch (board_id) {
360  case ADL_P_LP4_1:
361  case ADL_P_LP4_2:
362  return &lpddr4_mem_config;
363  case ADL_P_DDR4_1:
364  case ADL_P_DDR4_2:
365  return &ddr4_mem_config;
366  case ADL_P_DDR5_1:
367  case ADL_P_DDR5_2:
368  return &ddr5_mem_config;
369  case ADL_P_LP5_1:
370  case ADL_P_LP5_2:
371  return &lp5_mem_config;
372  case ADL_M_LP4:
373  return &adlm_lp4_mem_config;
374  case ADL_M_LP5:
375  return &adlm_lp5_mem_config;
376  case ADL_N_LP5:
377  return &adln_lp5_mem_config;
378  default:
379  die("unsupported board id : 0x%x\n", board_id);
380  }
381 }
MEM_TYPE_LP5X
@ MEM_TYPE_LP5X
Definition: meminit.h:14
MEM_TYPE_LP4X
@ MEM_TYPE_LP4X
Definition: meminit.h:13
MEM_TYPE_DDR5
@ MEM_TYPE_DDR5
Definition: meminit.h:12
MEM_TYPE_DDR4
@ MEM_TYPE_DDR4
Definition: meminit.h:11
die
void __noreturn die(const char *fmt,...)
Definition: die.c:17
board_id
uint32_t board_id(void)
board_id() - Get the board version
Definition: ec_boardid.c:6
ADL_M_LP4
@ ADL_M_LP4
Definition: variants.h:24
ADL_P_DDR5_2
@ ADL_P_DDR5_2
Definition: variants.h:16
ADL_P_LP4_1
@ ADL_P_LP4_1
Definition: variants.h:12
ADL_P_LP4_2
@ ADL_P_LP4_2
Definition: variants.h:13
ADL_N_LP5
@ ADL_N_LP5
Definition: variants.h:27
ADL_P_LP5_1
@ ADL_P_LP5_1
Definition: variants.h:18
ADL_P_DDR4_2
@ ADL_P_DDR4_2
Definition: variants.h:22
ADL_M_LP5
@ ADL_M_LP5
Definition: variants.h:25
ADL_P_DDR5_1
@ ADL_P_DDR5_1
Definition: variants.h:15
ADL_P_DDR4_1
@ ADL_P_DDR4_1
Definition: variants.h:21
ADL_P_LP5_2
@ ADL_P_LP5_2
Definition: variants.h:19
variant_memory_params
const struct mb_cfg *__weak variant_memory_params(void)
Definition: memory.c:67
get_board_id
static uint8_t get_board_id(void)
Definition: boardid.c:14
lpddr4_mem_config
static const struct mb_cfg lpddr4_mem_config
Definition: memory.c:31
lp5_mem_config
static const struct mb_cfg lp5_mem_config
Definition: memory.c:89
adlm_lp5_mem_config
static const struct mb_cfg adlm_lp5_mem_config
Definition: memory.c:233
ddr4_mem_config
static const struct mb_cfg ddr4_mem_config
Definition: memory.c:9
adlm_lp4_mem_config
static const struct mb_cfg adlm_lp4_mem_config
Definition: memory.c:173
ddr5_mem_config
static const struct mb_cfg ddr5_mem_config
Definition: memory.c:151
adln_lp5_mem_config
static const struct mb_cfg adln_lp5_mem_config
Definition: memory.c:293
BOARD_TYPE_ULT_ULX
@ BOARD_TYPE_ULT_ULX
Definition: romstage.h:16
BOARD_TYPE_MOBILE
@ BOARD_TYPE_MOBILE
Definition: romstage.h:14
BOARD_TYPE_ULT_ULX_T4
@ BOARD_TYPE_ULT_ULX_T4
Definition: romstage.h:17
mb_cfg
Definition: meminit.h:71
mb_cfg::type
enum mem_type type
Definition: meminit.h:72
board_id.h