coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <boardid.h>
4 #include <bootblock_common.h>
5 #include <gpio.h>
6 #include <device/mmio.h>
7 #include <soc/gpio.h>
8 #include <soc/i2c.h>
9 #include <soc/mt6391.h>
10 #include <soc/pericfg.h>
11 #include <soc/spi.h>
12 
13 #include "gpio.h"
14 
15 static void i2c_set_gpio_pinmux(void)
16 {
17  gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1);
18  gpio_set_mode(GPIO(SCL1), PAD_SCL1_FUNC_SCL1);
19  gpio_set_mode(GPIO(SDA4), PAD_SDA4_FUNC_SDA4);
20  gpio_set_mode(GPIO(SCL4), PAD_SCL4_FUNC_SCL4);
21 }
22 
23 static void nor_set_gpio_pinmux(void)
24 {
25  /* Set driving strength of EINT4~EINT9 to 8mA
26  * 0: 2mA
27  * 1: 4mA
28  * 2: 8mA
29  * 3: 16mA
30  */
31  /* EINT4: 0x10005B20[14:13] */
32  clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
33  /* EINT5~EINT9: 0x10005B30[2:1] */
34  clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
35 
42 
43  gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SFWP_B);
44  gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SFOUT);
45  gpio_set_mode(GPIO(EINT6), PAD_EINT6_FUNC_SFCS0);
46  gpio_set_mode(GPIO(EINT7), PAD_EINT7_FUNC_SFHOLD);
47  gpio_set_mode(GPIO(EINT8), PAD_EINT8_FUNC_SFIN);
48  gpio_set_mode(GPIO(EINT9), PAD_EINT9_FUNC_SFCK);
49 }
50 
52 {
53  /* Clear UART0 power down signal */
55 }
56 
58 {
59  /* adjust gpio params when external voltage is 1.8V */
61 
62  /* set i2c related gpio */
64 
65  /* set nor related GPIO */
67 
68  /* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
69  if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
70  board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
71  gpio_output(GPIO(SRCLKENAI2), 1);
72 
73  /* Init i2c bus 2 Timing register for TPM */
74  mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
75 
76  mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
77  0);
78 
80 
81  if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 4)
83 }
#define MHz
Definition: helpers.h:80
@ GPIO
Definition: chip.h:84
uint32_t board_id(void)
board_id() - Get the board version
Definition: ec_boardid.c:6
void setup_chromeos_gpios(void)
Definition: chromeos.c:10
#define clrsetbits16(addr, clear, set)
Definition: mmio.h:15
#define clrbits32(addr, clear)
Definition: mmio.h:26
void gpio_output(gpio_t gpio, int value)
Definition: gpio.c:194
__weak void bootblock_mainboard_init(void)
Definition: bootblock.c:19
__weak void bootblock_mainboard_early_init(void)
Definition: bootblock.c:16
static void nor_set_gpio_pinmux(void)
Definition: bootblock.c:23
static void i2c_set_gpio_pinmux(void)
Definition: bootblock.c:15
static void gpio_init(pnp_devfn_t dev)
Definition: bootblock.c:19
@ GPIO_PULL_ENABLE
Definition: gpio_common.h:13
void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select)
Definition: gpio.c:17
void mt6391_enable_reset_when_ap_resets(void)
Definition: mt6391.c:84
static struct mt8173_pericfg_regs *const mt8173_pericfg
Definition: pericfg.h:68
@ PERICFG_UART0_PDN
Definition: pericfg.h:76
void gpio_set_mode(gpio_t gpio, int mode)
Definition: gpio.c:45
void mtk_i2c_bus_init(uint8_t bus)
Definition: i2c.c:65
static struct gpio_regs *const mtk_gpio
Definition: gpio.h:347
@ GPIO_EINT_1P8V
Definition: gpio.h:17
#define GPIO_PULL_UP
Definition: gpio.h:24
@ SPI_PAD1_MASK
Definition: spi_common.h:47
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, unsigned int speed_hz, unsigned int tick_dly)
Definition: spi.c:56
struct val_regs drv_mode[10]
Definition: gpio.h:332
uint32_t val
Definition: gpio.h:306