coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | intel_spi_op |
struct | intel_swseq_spi_config |
Enumerations | |
enum | optype { READ_NO_ADDR = 0 , WRITE_NO_ADDR = 1 , READ_WITH_ADDR = 2 , WRITE_WITH_ADDR = 3 } |
Functions | |
void | spi_finalize_ops (void) |
void | intel_southbridge_override_spi (struct intel_swseq_spi_config *spi_config) |
enum optype |
void intel_southbridge_override_spi | ( | struct intel_swseq_spi_config * | spi_config | ) |
Definition at line 645 of file lpc.c.
Referenced by spi_finalize_ops().
Definition at line 1039 of file spi.c.
References ARRAY_SIZE, boot_device_spi_flash(), cntlr, CONFIG, intel_southbridge_override_spi(), spi_flash::model, ich_spi_controller::opmenu, ich_spi_controller::optype, ich_spi_controller::preop, READ_NO_ADDR, READ_WITH_ADDR, spi_locked(), spi_set_smm_only_flashing(), spi_flash::vendor, VENDOR_ID_SST, WRITE_NO_ADDR, WRITE_WITH_ADDR, writeb_, and writew_.
Referenced by broadwell_pch_finalize(), finalize_chipset(), and lpc_final().