coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
spi.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_SPI_H
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#define SOUTHBRIDGE_INTEL_SPI_H
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enum
optype
{
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READ_NO_ADDR
= 0,
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WRITE_NO_ADDR
= 1,
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READ_WITH_ADDR
= 2,
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WRITE_WITH_ADDR
= 3
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};
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struct
intel_spi_op
{
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u8
op
;
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enum
optype
type
;
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};
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struct
intel_swseq_spi_config
{
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u8
opprefixes
[2];
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struct
intel_spi_op
ops
[8];
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};
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void
spi_finalize_ops
(
void
);
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void
intel_southbridge_override_spi
(
struct
intel_swseq_spi_config
*
spi_config
);
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#endif
spi_finalize_ops
void spi_finalize_ops(void)
Definition:
spi.c:1039
optype
optype
Definition:
spi.h:7
WRITE_WITH_ADDR
@ WRITE_WITH_ADDR
Definition:
spi.h:11
READ_WITH_ADDR
@ READ_WITH_ADDR
Definition:
spi.h:10
READ_NO_ADDR
@ READ_NO_ADDR
Definition:
spi.h:8
WRITE_NO_ADDR
@ WRITE_NO_ADDR
Definition:
spi.h:9
intel_southbridge_override_spi
void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
Definition:
lpc.c:645
u8
uint8_t u8
Definition:
stdint.h:45
intel_spi_op
Definition:
spi.h:14
intel_spi_op::op
u8 op
Definition:
spi.h:15
intel_spi_op::type
enum optype type
Definition:
spi.h:16
intel_swseq_spi_config
Definition:
spi.h:19
intel_swseq_spi_config::opprefixes
u8 opprefixes[2]
Definition:
spi.h:20
intel_swseq_spi_config::ops
struct intel_spi_op ops[8]
Definition:
spi.h:21
spi_config
Definition:
spi.h:77
src
southbridge
intel
common
spi.h
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