coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mainboard.c File Reference
#include <amdblocks/acpimmio.h>
#include <amdblocks/acpimmio_legacy_gpio100.h>
#include <console/console.h>
#include <device/device.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <vendorcode/amd/cimx/sb800/OEM.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include "sema.h"
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Macros

#define SIO_RUNTIME_BASE   0x0E00
 

Functions

static void pirq_setup (void)
 
static void init (struct device *dev)
 
static void mainboard_enable (struct device *dev)
 

Variables

static const u8 mainboard_intr_data []
 
static const u16 sio_init_table []
 
struct chip_operations mainboard_ops
 

Macro Definition Documentation

◆ SIO_RUNTIME_BASE

#define SIO_RUNTIME_BASE   0x0E00

Definition at line 28 of file mainboard.c.

Function Documentation

◆ init()

static void init ( struct device dev)
static

Definition at line 64 of file mainboard.c.

References ARRAY_SIZE, BIOS_DEBUG, BIOS_INFO, fch_gpio_state(), gpio_100_write8(), GPIO_BASE, iomux_write8(), outb(), pci_read_config32(), pcidev_on_root(), printk, sema_send_alive(), sio_init_table, SIO_RUNTIME_BASE, spi_base, and val.

Referenced by mainboard_enable().

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◆ mainboard_enable()

static void mainboard_enable ( struct device dev)
static

Definition at line 131 of file mainboard.c.

References init(), device_operations::init, misc_write8(), device::ops, pirq_setup(), and pm_write8().

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◆ pirq_setup()

static void pirq_setup ( void  )
static

Definition at line 59 of file mainboard.c.

References intr_data_ptr, and mainboard_intr_data.

Referenced by mainboard_enable().

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Variable Documentation

◆ mainboard_intr_data

const u8 mainboard_intr_data[]
static
Initial value:
= {
[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x11, 0x12, 0x13
}

Definition at line 17 of file mainboard.c.

Referenced by pirq_setup().

◆ mainboard_ops

struct chip_operations mainboard_ops
Initial value:
= {
.enable_dev = mainboard_enable,
}
static void mainboard_enable(struct device *dev)
Definition: mainboard.c:131

Definition at line 131 of file mainboard.c.

◆ sio_init_table

const u16 sio_init_table[]
static
Initial value:
= {
0x4BA0,
0x2300,
0x2400,
0x2500,
0x2600,
0x2700,
0x2900,
0x2A00,
0x2B00,
0x3904,
0x4E74,
0x6E84,
0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
0x470C,
0x5E00,
0x4884,
0x5038,
0x5580,
0x5680,
0x5780,
}

Definition at line 29 of file mainboard.c.

Referenced by init().