3 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
4 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
9 #define PCH_TYPE_CPT 0x1c
10 #define PCH_TYPE_PPT 0x1e
20 #define SMBUS_SLAVE_ADDR 0x24
22 #define DEFAULT_GPIOBASE 0x0480
23 #define DEFAULT_PMBASE 0x0500
27 #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X)
28 #define CROS_GPIO_DEVICE_NAME "CougarPoint"
29 #elif CONFIG(SOUTHBRIDGE_INTEL_C216)
30 #define CROS_GPIO_DEVICE_NAME "PantherPoint"
69 #define UPRWC_WR_EN (1 << 1)
77 #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
78 #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
79 #define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
80 #define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6)
81 #define PCH_PCIE_DEV_SLOT 28
82 #define PCH_IOAPIC_PCI_BUS 250
83 #define PCH_IOAPIC_PCI_SLOT 31
84 #define PCH_HPET_PCI_BUS 250
85 #define PCH_HPET_PCI_SLOT 15
88 #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
90 #define XHCI_PWR_CNTL_STS 0x74
93 #define XHCI_PORTSC_x_USB3(port) (0x4c0 + (port) * 0x10)
96 #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
97 #define SERIRQ_CNTL 0x64
99 #define GEN_PMCON_1 0xa0
100 #define GEN_PMCON_2 0xa2
101 #define GEN_PMCON_3 0xa4
102 #define GEN_PMCON_LOCK 0xa6
104 #define ETR3_CWORWRE (1 << 18)
105 #define ETR3_CF9GR (1 << 20)
106 #define ETR3_CF9LOCK (1 << 31)
109 #define RTC_BATTERY_DEAD (1 << 2)
110 #define RTC_POWER_FAILED (1 << 1)
111 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
114 #define ACPI_CNTL 0x44
115 #define ACPI_EN (1 << 7)
116 #define BIOS_CNTL 0xDC
117 #define GPIO_BASE 0x48
118 #define GPIO_CNTL 0x4C
120 #define GPIO_ROUT 0xb8
121 #define GPI_DISABLE 0x00
122 #define GPI_IS_SMI 0x01
123 #define GPI_IS_SCI 0x02
124 #define GPI_IS_NMI 0x03
126 #define PIRQA_ROUT 0x60
127 #define PIRQB_ROUT 0x61
128 #define PIRQC_ROUT 0x62
129 #define PIRQD_ROUT 0x63
130 #define PIRQE_ROUT 0x68
131 #define PIRQF_ROUT 0x69
132 #define PIRQG_ROUT 0x6A
133 #define PIRQH_ROUT 0x6B
135 #define LPC_IBDF 0x6C
136 #define LPC_HnBDF(n) (0x70 + n * 2)
138 #define LPC_IO_DEC 0x80
140 #define CNF2_LPC_EN (1 << 13)
141 #define CNF1_LPC_EN (1 << 12)
142 #define MC_LPC_EN (1 << 11)
143 #define KBC_LPC_EN (1 << 10)
144 #define GAMEH_LPC_EN (1 << 9)
145 #define GAMEL_LPC_EN (1 << 8)
146 #define FDD_LPC_EN (1 << 3)
147 #define LPT_LPC_EN (1 << 2)
148 #define COMB_LPC_EN (1 << 1)
149 #define COMA_LPC_EN (1 << 0)
150 #define LPC_GEN1_DEC 0x84
151 #define LPC_GEN2_DEC 0x88
152 #define LPC_GEN3_DEC 0x8c
153 #define LPC_GEN4_DEC 0x90
155 #define BIOS_DEC_EN1 0xd8
158 #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
159 #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
160 #define IDE_TIM_PRI 0x40
161 #define IDE_DECODE_ENABLE (1 << 15)
162 #define IDE_TIM_SEC 0x42
164 #define SATA_SIRI 0xa0
165 #define SATA_SIRD 0xa4
169 #define SATA_IOBP_SP0G3IR 0xea000151
170 #define SATA_IOBP_SP1G3IR 0xea000051
173 #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
174 #define SMB_BASE 0x20
178 #define I2C_EN (1 << 2)
179 #define SMB_SMI_EN (1 << 1)
180 #define HST_EN (1 << 0)
184 #define GPIOBASE 0x48
189 #define TCLOCKDN (1u << 31)
199 #define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
201 #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
203 #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
205 #define RPFN_FNMASK(port) (7 << ((port) * 4))
252 #define DLCTL2 0x21b0
262 #define IOBPIRI 0x2330
265 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
266 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
267 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
270 #define D31IP_TTIP 24
271 #define D31IP_SIP2 20
272 #define D31IP_SMIP 12
279 #define D28IP_P8IP 28
280 #define D28IP_P7IP 24
281 #define D28IP_P6IP 20
282 #define D28IP_P5IP 16
283 #define D28IP_P4IP 12
294 #define D22IP_KTIP 12
295 #define D22IP_IDERIP 8
296 #define D22IP_MEI2IP 4
297 #define D22IP_MEI1IP 0
299 #define D20IP_XHCIIP 0
310 #define SOFT_RESET_CTRL 0x38f4
311 #define SOFT_RESET_DATA 0x38f8
313 #define DIR_ROUTE(x,a,b,c,d) \
314 RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
315 ((b) << DIR_IBR) | ((a) << DIR_IAR))
319 #define PM_CFG 0x3318
332 #define PMSYNC_CFG 0x33c8
341 #define PCH_DISABLE_GBE (1 << 5)
343 #define DISPBDF 0x3424
348 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
349 #define PCH_DISABLE_P2P (1 << 1)
350 #define PCH_DISABLE_SATA1 (1 << 2)
351 #define PCH_DISABLE_SMBUS (1 << 3)
352 #define PCH_DISABLE_HD_AUDIO (1 << 4)
353 #define PCH_DISABLE_EHCI2 (1 << 13)
354 #define PCH_DISABLE_LPC (1 << 14)
355 #define PCH_DISABLE_EHCI1 (1 << 15)
356 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
357 #define PCH_DISABLE_THERMAL (1 << 24)
358 #define PCH_DISABLE_SATA2 (1 << 25)
359 #define PCH_DISABLE_XHCI (1 << 27)
362 #define PCH_DISABLE_KT (1 << 4)
363 #define PCH_DISABLE_IDER (1 << 3)
364 #define PCH_DISABLE_MEI2 (1 << 2)
365 #define PCH_DISABLE_MEI1 (1 << 1)
366 #define PCH_ENABLE_DBDF (1 << 0)
369 #define USBIR0 0x3500
370 #define USBIR1 0x3504
371 #define USBIR2 0x3508
372 #define USBIR3 0x350c
373 #define USBIR4 0x3510
374 #define USBIR5 0x3514
375 #define USBIR6 0x3518
376 #define USBIR7 0x351c
377 #define USBIR8 0x3520
378 #define USBIR9 0x3524
379 #define USBIR10 0x3528
380 #define USBIR11 0x352c
381 #define USBIR12 0x3530
382 #define USBIR13 0x3534
385 #define MISCCTL 0x3590
387 #define USBPDO 0x359c
389 #define USBOCM1 0x35a0
390 #define USBOCM2 0x35a4
392 #define RMHWKCTL 0x35b0
403 #define XUSB2PRM 0xd4
408 #define WAK_STS (1 << 15)
409 #define PCIEXPWAK_STS (1 << 14)
410 #define PRBTNOR_STS (1 << 11)
411 #define RTC_STS (1 << 10)
412 #define PWRBTN_STS (1 << 8)
413 #define GBL_STS (1 << 5)
414 #define BM_STS (1 << 4)
415 #define TMROF_STS (1 << 0)
417 #define PCIEXPWAK_DIS (1 << 14)
418 #define RTC_EN (1 << 10)
419 #define PWRBTN_EN (1 << 8)
420 #define GBL_EN (1 << 5)
421 #define TMROF_EN (1 << 0)
423 #define GBL_RLS (1 << 2)
424 #define BM_RLD (1 << 1)
425 #define SCI_EN (1 << 0)
427 #define PROC_CNT 0x10
432 #define GPE0_STS 0x20
433 #define PME_B0_STS (1 << 13)
434 #define PME_STS (1 << 11)
435 #define BATLOW_STS (1 << 10)
436 #define PCI_EXP_STS (1 << 9)
437 #define RI_STS (1 << 8)
438 #define SMB_WAK_STS (1 << 7)
439 #define TCOSCI_STS (1 << 6)
440 #define SWGPE_STS (1 << 2)
441 #define HOT_PLUG_STS (1 << 1)
443 #define PME_B0_EN (1 << 13)
444 #define PME_EN (1 << 11)
445 #define TCOSCI_EN (1 << 6)
447 #define INTEL_USB2_EN (1 << 18)
448 #define LEGACY_USB2_EN (1 << 17)
449 #define PERIODIC_EN (1 << 14)
450 #define TCO_EN (1 << 13)
451 #define MCSMI_EN (1 << 11)
452 #define BIOS_RLS (1 << 7)
453 #define SWSMI_TMR_EN (1 << 6)
454 #define APMC_EN (1 << 5)
455 #define SLP_SMI_EN (1 << 4)
456 #define LEGACY_USB_EN (1 << 3)
457 #define BIOS_EN (1 << 2)
459 #define GBL_SMI_EN (1 << 0)
461 #define ALT_GP_SMI_EN 0x38
462 #define ALT_GP_SMI_STS 0x3a
463 #define GPE_CNTL 0x42
464 #define DEVACT_STS 0x44
467 #define TCO1_STS 0x64
468 #define TCO1_TIMEOUT (1 << 3)
469 #define DMISCI_STS (1 << 9)
470 #define TCO2_STS 0x66
471 #define SECOND_TO_STS (1 << 1)
472 #define TCO1_CNT 0x68
473 #define TCO_TMR_HLT (1 << 11)
474 #define TCO_LOCK (1 << 12)
475 #define TCO2_CNT 0x6a
477 #define SPIBAR_HSFS 0x3804
478 #define SPIBAR_HSFS_SCIP (1 << 5)
479 #define SPIBAR_HSFS_AEL (1 << 2)
480 #define SPIBAR_HSFS_FCERR (1 << 1)
481 #define SPIBAR_HSFS_FDONE (1 << 0)
482 #define SPIBAR_HSFC 0x3806
483 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
484 #define SPIBAR_HSFC_CYCLE_READ (0 << 1)
485 #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1)
486 #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1)
487 #define SPIBAR_HSFC_GO (1 << 0)
488 #define SPIBAR_FADDR 0x3808
489 #define SPIBAR_FDATA(n) (0x3810 + (4 * n))
void early_thermal_init(void)
void southbridge_configure_default_intmap(void)
void early_pch_init(void)
void early_pch_init_native(void)
void early_pch_init_native_dmi_pre(void)
void early_pch_init_native_dmi_post(void)
void enable_usb_bar(void)
void mainboard_late_rcba_config(void)
void southbridge_rcba_config(void)
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
void early_usb_init(const struct southbridge_usb_port *portmap)
void pch_enable(struct device *dev)
void mainboard_pch_lpc_setup(void)
int pch_silicon_type(void)
int pch_silicon_revision(void)
const struct southbridge_usb_port mainboard_usb_ports[14]