coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_usb_mrc.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/pci_ops.h>
4 #include <device/pci_def.h>
5 #include "pch.h"
6 
7 #define PCH_EHCI1_TEMP_BAR0 0xe8000000
8 #define PCH_EHCI2_TEMP_BAR0 0xe8000400
9 
10 /*
11  * Setup USB controller MMIO BAR to prevent the
12  * reference code from resetting the controller.
13  *
14  * The BAR will be re-assigned during device
15  * enumeration so these are only temporary.
16  */
17 void enable_usb_bar(void)
18 {
21 
22  /* USB Controller 1 */
26 
27  /* USB Controller 2 */
31 }
void enable_usb_bar(void)
Definition: early_usb_mrc.c:17
#define PCH_EHCI1_TEMP_BAR0
Definition: early_usb_mrc.c:7
#define PCH_EHCI2_TEMP_BAR0
Definition: early_usb_mrc.c:8
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
Definition: pci_ops.h:180
#define PCI_COMMAND_MASTER
Definition: pci_def.h:13
#define PCI_COMMAND_MEMORY
Definition: pci_def.h:12
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define PCI_COMMAND
Definition: pci_def.h:10
u32 pci_devfn_t
Definition: pci_type.h:8
#define PCH_EHCI1_DEV
Definition: pch.h:77
#define PCH_EHCI2_DEV
Definition: pch.h:78