dsi_pll_regs Struct Reference

Collaboration diagram for dsi_pll_regs:

Data Fields
u32	pll_prop_gain_rate
u32	decimal_div_start
u32	frac_div_start_low
u32	frac_div_start_mid
u32	frac_div_start_high
u32	pll_clock_inverters

Detailed Description

Definition at line 16 of file dsi_phy_pll.c.

Field Documentation

decimal_div_start

u32 dsi_pll_regs::decimal_div_start

Definition at line 18 of file dsi_phy_pll.c.

Referenced by dsi_pll_commit().

frac_div_start_high

u32 dsi_pll_regs::frac_div_start_high

Definition at line 21 of file dsi_phy_pll.c.

Referenced by dsi_pll_commit().

frac_div_start_low

u32 dsi_pll_regs::frac_div_start_low

Definition at line 19 of file dsi_phy_pll.c.

Referenced by dsi_pll_commit().

frac_div_start_mid

u32 dsi_pll_regs::frac_div_start_mid

Definition at line 20 of file dsi_phy_pll.c.

Referenced by dsi_pll_commit().

pll_clock_inverters

u32 dsi_pll_regs::pll_clock_inverters

Definition at line 22 of file dsi_phy_pll.c.

Referenced by dsi_pll_commit().

pll_prop_gain_rate

u32 dsi_pll_regs::pll_prop_gain_rate

Definition at line 17 of file dsi_phy_pll.c.

Referenced by dsi_pll_config_hzindep_reg().

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The documentation for this struct was generated from the following file:

• src/soc/qualcomm/sc7180/display/dsi_phy_pll.c