10 #define VCO_DELAY_USEC 1
13 #define SSC_CENTER BIT(0)
72 u64 dec, dec_multiple;
79 multiplier = 1 << frac_bits;
80 dec_multiple = (pll_freq * multiplier) / divider;
81 frac = dec_multiple % multiplier;
83 dec = dec_multiple / multiplier;
84 if (pll_freq <= 1900UL *
MHz)
85 regs->pll_prop_gain_rate = 8;
86 else if (pll_freq <= 3000UL *
MHz)
87 regs->pll_prop_gain_rate = 10;
89 regs->pll_prop_gain_rate = 12;
91 if (pll_freq < 1100UL *
MHz)
92 regs->pll_clock_inverters = 8;
94 regs->pll_clock_inverters = 0;
96 regs->decimal_div_start = dec;
97 regs->frac_div_start_low = (frac & 0xff);
98 regs->frac_div_start_mid = (frac & 0xff00) >> 8;
99 regs->frac_div_start_high = (frac & 0x30000) >> 16;
static void write32(void *addr, uint32_t val)
static void dsi_pll_commit(struct dsi_pll_regs *reg)
void dsi_phy_pll_vco_10nm_set_rate(unsigned long rate)
static void dsi_pll_init_val(void)
static void dsi_pll_config_hzindep_reg(struct dsi_pll_regs *reg)
static void dsi_pll_calc_dec_frac(struct dsi_pll_regs *regs, unsigned long rate)
static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink
uint32_t pll_feedback_divider
uint32_t pll_core_input_override
uint32_t pll_freq_update_ctrl_overrides
uint32_t pll_fastlock_ctrl
uint32_t pll_frac_div_start_high1
uint32_t pll_cal_settings
uint32_t pll_band_sel_cal_settings
uint32_t pll_core_override
uint32_t pll_lock_min_delay
uint32_t pll_digital_timers_two
uint32_t pll_gain_ifilt_band[2]
uint32_t pll_lock_override
uint32_t pll_band_sel_pfilt
uint32_t pll_band_sel_cal_settings_three
uint32_t pll_int_loop_settings
uint32_t pll_int_loop_settings_two
uint32_t pll_freq_tune_accum_init_mux
uint32_t pll_lockdet_rate[2]
uint32_t pll_band_sel_ifilt
uint32_t pll_pass_out_override_two
uint32_t pll_decimal_div_start_1
uint32_t pll_frac_div_start_mid1
uint32_t pll_band_sel_cal_timer_low
uint32_t pll_band_sel_icode_low
uint32_t pll_ssc_mux_ctrl
uint32_t pll_alog_obsv_bus_ctrl_1
uint32_t pll_band_sel_cal_settings_two
uint32_t pll_band_sel_cal_timer_high
uint32_t pll_band_set_rate[2]
uint32_t pll_freq_detect_settings_one
uint32_t pll_clock_inverters
uint32_t pll_frac_div_start_low1
uint32_t pll_analog_ctrls_one
uint32_t pll_band_sel_min
uint32_t pll_analog_ctrls_three
uint32_t pll_fl_int_gain_pfilt_band[2]
uint32_t pll_band_sel_max
uint32_t pll_analog_ctrls_four
uint32_t pll_dec_frac_muxes
uint32_t pll_pass_out_override_one
uint32_t pll_band_sel_icode_high
uint32_t pll_band_sel_cal_settings_four
uint32_t pll_pll_fastlock_en_band
uint32_t pll_int_loop_ctrls
uint32_t pll_spare_and_jpc_overrides
uint32_t pll_prop_gain_rate[2]
uint32_t pll_analog_ctrls_two
uint32_t pll_digital_timers