coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ddr4.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /*
4  * JEDEC Standard No. 21-C
5  * Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
6  */
7 
8 #ifndef DEVICE_DRAM_DDR4L_H
9 #define DEVICE_DRAM_DDR4L_H
10 
11 /**
12  * @file ddr4.h
13  *
14  * \brief Utilities for decoding DDR4 SPDs
15  */
16 
17 #include <spd.h>
18 #include <device/dram/common.h>
19 #include <types.h>
20 
21 #define SPD_DDR4_PART_OFF 329
22 #define SPD_DDR4_PART_LEN 20
23 
24 /*
25  * Module type (byte 3, bits 3:0) of SPD
26  * This definition is specific to DDR4. DDR2/3 SPDs have a different structure.
27  */
40  /* Masks to bits 3:0 to give the dimm type */
42 };
43 
44 /**
45  * \brief DIMM characteristics
46  *
47  * The characteristics of each DIMM, as presented by the SPD
48  */
62 };
63 
64 typedef u8 spd_raw_data[512];
65 
66 int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd);
67 
68 enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
69  const u16 selected_freq,
70  const struct dimm_attr_ddr4_st *info);
71 
72 /**
73  * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
74  */
76 
77 #endif /* DEVICE_DRAM_DDR4L_H */
cb_err
coreboot error codes
Definition: cb_err.h:15
int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
Decode the raw SPD data.
Definition: ddr4.c:166
uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
Converts DDR4 clock speed in MHz to the standard reported speed in MT/s.
Definition: ddr4.c:137
u8 spd_raw_data[512]
Definition: ddr4.h:64
enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, const struct dimm_attr_ddr4_st *info)
Definition: ddr4.c:263
spd_dimm_type_ddr4
Definition: ddr4.h:28
@ SPD_DDR4_DIMM_TYPE_SO_DIMM
Definition: ddr4.h:32
@ SPD_DDR4_DIMM_TYPE_32B_SO_DIMM
Definition: ddr4.h:39
@ SPD_DDR4_DIMM_TYPE_UDIMM
Definition: ddr4.h:31
@ SPD_DDR4_DIMM_TYPE_EXTENDED
Definition: ddr4.h:29
@ SPD_DDR4_DIMM_TYPE_RDIMM
Definition: ddr4.h:30
@ SPD_DDR4_DIMM_TYPE_MASK
Definition: ddr4.h:41
@ SPD_DDR4_DIMM_TYPE_16B_SO_DIMM
Definition: ddr4.h:38
@ SPD_DDR4_DIMM_TYPE_LRDIMM
Definition: ddr4.h:33
@ SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM
Definition: ddr4.h:37
@ SPD_DDR4_DIMM_TYPE_MINI_RDIMM
Definition: ddr4.h:34
@ SPD_DDR4_DIMM_TYPE_MINI_UDIMM
Definition: ddr4.h:35
@ SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM
Definition: ddr4.h:36
#define SPD_DDR4_PART_LEN
Definition: ddr4.h:22
static struct smmstore_params_info info
Definition: ramstage.c:12
spd_memory_type
Definition: spd.h:140
unsigned short uint16_t
Definition: stdint.h:11
uint16_t u16
Definition: stdint.h:48
uint8_t u8
Definition: stdint.h:45
DIMM characteristics.
Definition: ddr4.h:49
u8 serial_number[4]
Definition: ddr4.h:53
u16 manufacturer_id
Definition: ddr4.h:59
char part_number[SPD_DDR4_PART_LEN+1]
Definition: ddr4.h:52
enum spd_memory_type dram_type
Definition: ddr4.h:50
enum spd_dimm_type_ddr4 dimm_type
Definition: ddr4.h:51
u16 cap_per_die_mbit
Definition: ddr4.h:57
u16 vdd_voltage
Definition: ddr4.h:60
bool ecc_extension
Definition: ddr4.h:61
u8 sdram_width
Definition: ddr4.h:56