sn65dsi86bridge.c File Reference

#include <console/console.h>
#include <endian.h>
#include <device/i2c_simple.h>
#include <dp_aux.h>
#include <edid.h>
#include <timer.h>
#include <types.h>
#include <soc/addressmap.h>
#include "sn65dsi86bridge.h"

Include dependency graph for sn65dsi86bridge.c:

Go to the source code of this file.

Macros
#define	BRIDGE_GETHIGHERBYTE(x)   ((uint8_t)((x & 0xff00) >> 8))
#define	BRIDGE_GETLOWERBYTE(x)   ((uint8_t)(x & 0x00ff))
#define	DP_CLK_FUDGE_NUM   10
#define	DP_CLK_FUDGE_DEN   8
#define	DP_BRIDGE_DPCD_REV   0x700
#define	DP_BRIDGE_11   0x00
#define	DP_BRIDGE_12   0x01
#define	DP_BRIDGE_13   0x02
#define	DP_BRIDGE_14   0x03
#define	DP_BRIDGE_CONFIGURATION_SET   0x10a
#define	DP_MAX_LINK_RATE   0x001
#define	DP_MAX_LANE_COUNT   0x002
#define	DP_SUPPORTED_LINK_RATES   0x010 /* eDP 1.4 */
#define	DP_MAX_LINK_RATE   0x001
#define	DP_MAX_SUPPORTED_RATES   8 /* 16-bit little-endian */
#define	DP_LANE_COUNT_MASK   0xf
#define	DP_LINK_BW_SET   0x100
#define	DP_LINK_BW_1_62   0x06
#define	DP_LINK_BW_2_7   0x0a
#define	DP_LINK_BW_5_4   0x14
#define	AUX_CMD_SEND   0x1
#define	MIN_DSI_CLK_FREQ_MHZ   40
#define	MAX_DSI_CLK_FREQ_MHZ   750

Enumerations
enum	bridge_regs {   SN_DPPLL_SRC_REG = 0x0A , SN_PLL_ENABLE_REG = 0x0D , SN_DSI_LANES_REG = 0x10 , SN_DSIA_CLK_FREQ_REG = 0x12 ,   SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG = 0x20 , SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG = 0x21 , SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG = 0x24 , SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG = 0x25 ,   SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG = 0x2C , SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG = 0x2D , SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG = 0x30 , SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG = 0x31 ,   SN_CHA_HORIZONTAL_BACK_PORCH_REG = 0x34 , SN_CHA_VERTICAL_BACK_PORCH_REG = 0x36 , SN_CHA_HORIZONTAL_FRONT_PORCH_REG = 0x38 , SN_CHA_VERTICAL_FRONT_PORCH_REG = 0x3A ,   SN_COLOR_BAR_REG = 0x3C , SN_ENH_FRAME_REG = 0x5A , SN_DATA_FORMAT_REG = 0x5B , SN_HPD_DISABLE_REG = 0x5C ,   SN_I2C_CLAIM_ADDR_EN1 = 0x60 , SN_AUX_WDATA_REG_0 = 0x64 , SN_AUX_WDATA_REG_1 = 0x65 , SN_AUX_WDATA_REG_2 = 0x66 ,   SN_AUX_WDATA_REG_3 = 0x67 , SN_AUX_WDATA_REG_4 = 0x68 , SN_AUX_WDATA_REG_5 = 0x69 , SN_AUX_WDATA_REG_6 = 0x6A ,   SN_AUX_WDATA_REG_7 = 0x6B , SN_AUX_WDATA_REG_8 = 0x6C , SN_AUX_WDATA_REG_9 = 0x6D , SN_AUX_WDATA_REG_10 = 0x6E ,   SN_AUX_WDATA_REG_11 = 0x6F , SN_AUX_WDATA_REG_12 = 0x70 , SN_AUX_WDATA_REG_13 = 0x71 , SN_AUX_WDATA_REG_14 = 0x72 ,   SN_AUX_WDATA_REG_15 = 0x73 , SN_AUX_ADDR_19_16_REG = 0x74 , SN_AUX_ADDR_15_8_REG = 0x75 , SN_AUX_ADDR_7_0_REG = 0x76 ,   SN_AUX_LENGTH_REG = 0x77 , SN_AUX_CMD_REG = 0x78 , SN_AUX_RDATA_REG_0 = 0x79 , SN_AUX_RDATA_REG_1 = 0x7A ,   SN_AUX_RDATA_REG_2 = 0x7B , SN_AUX_RDATA_REG_3 = 0x7C , SN_AUX_RDATA_REG_4 = 0x7D , SN_AUX_RDATA_REG_5 = 0x7E ,   SN_AUX_RDATA_REG_6 = 0x7F , SN_AUX_RDATA_REG_7 = 0x80 , SN_AUX_RDATA_REG_8 = 0x81 , SN_AUX_RDATA_REG_9 = 0x82 ,   SN_AUX_RDATA_REG_10 = 0x83 , SN_AUX_RDATA_REG_11 = 0x84 , SN_AUX_RDATA_REG_12 = 0x85 , SN_AUX_RDATA_REG_13 = 0x86 ,   SN_AUX_RDATA_REG_14 = 0x87 , SN_AUX_RDATA_REG_15 = 0x88 , SN_SSC_CONFIG_REG = 0x93 , SN_DATARATE_CONFIG_REG = 0x94 ,   SN_ML_TX_MODE_REG = 0x96 , SN_AUX_CMD_STATUS_REG = 0xF4 }
enum	{ HPD_ENABLE = 0x0 , HPD_DISABLE = 0x1 }
enum	{   SOT_ERR_TOL_DSI = 0x0 , CHB_DSI_LANES = 0x1 , CHA_DSI_LANES = 0x2 , DSI_CHANNEL_MODE = 0x3 ,   LEFT_RIGHT_PIXELS = 0x4 }
enum	vstream_config { VSTREAM_DISABLE = 0 , VSTREAM_ENABLE = 1 }
enum	aux_cmd_status {   NAT_I2C_FAIL = 1 << 6 , AUX_SHORT = 1 << 5 , AUX_DFER = 1 << 4 , AUX_RPLY_TOUT = 1 << 3 ,   SEND_INT = 1 << 0 }
enum	ml_tx_mode {   MAIN_LINK_OFF = 0x0 , NORMAL_MODE = 0x1 , TPS1 = 0x2 , TPS2 = 0x3 ,   TPS3 = 0x4 , PRBS7 = 0x5 , HBR2_COMPLIANCE_EYE_PATTERN = 0x6 , SYMBOL_ERR_RATE_MEASUREMENT_PATTERN = 0x7 ,   CUTSOM_PATTERN = 0x8 , FAST_LINK_TRAINING = 0x9 , SEMI_AUTO_LINK_TRAINING = 0xa , REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb }

Functions
static enum cb_err	sn65dsi86_bridge_aux_request (uint8_t bus, uint8_t chip, unsigned int target_reg, unsigned int total_size, enum aux_request request, uint8_t *data)
enum cb_err	sn65dsi86_bridge_read_edid (uint8_t bus, uint8_t chip, struct edid *out)
static void	sn65dsi86_bridge_valid_dp_rates (uint8_t bus, uint8_t chip, bool rate_valid[])
static void	sn65dsi86_bridge_set_dsi_clock_range (uint8_t bus, uint8_t chip, struct edid *edid, uint32_t num_of_lanes, uint32_t bpp)
static void	sn65dsi86_bridge_set_dp_clock_range (uint8_t bus, uint8_t chip, struct edid *edid, uint32_t num_of_lanes)
static void	sn65dsi86_bridge_set_bridge_active_timing (uint8_t bus, uint8_t chip, struct edid *edid)
static void	sn65dsi86_bridge_link_training (uint8_t bus, uint8_t chip)
void	sn65dsi86_backlight_enable (uint8_t bus, uint8_t chip)
static void	sn65dsi86_bridge_assr_config (uint8_t bus, uint8_t chip, int enable)
static int	sn65dsi86_bridge_dp_lane_config (uint8_t bus, uint8_t chip)
void	sn65dsi86_bridge_init (uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk)
void	sn65dsi86_bridge_configure (uint8_t bus, uint8_t chip, struct edid *edid, uint32_t num_of_lanes, uint32_t dsi_bpp)

Variables
static const unsigned int	sn65dsi86_bridge_dp_rate_lut []

Macro Definition Documentation

AUX_CMD_SEND

#define AUX_CMD_SEND   0x1

Definition at line 40 of file sn65dsi86bridge.c.

BRIDGE_GETHIGHERBYTE

#define BRIDGE_GETHIGHERBYTE

(

x

)

((uint8_t)((x & 0xff00) >> 8))

Definition at line 13 of file sn65dsi86bridge.c.

BRIDGE_GETLOWERBYTE

#define BRIDGE_GETLOWERBYTE

(

x

)

((uint8_t)(x & 0x00ff))

Definition at line 14 of file sn65dsi86bridge.c.

DP_BRIDGE_11

#define DP_BRIDGE_11   0x00

Definition at line 22 of file sn65dsi86bridge.c.

DP_BRIDGE_12

#define DP_BRIDGE_12   0x01

Definition at line 23 of file sn65dsi86bridge.c.

DP_BRIDGE_13

#define DP_BRIDGE_13   0x02

Definition at line 24 of file sn65dsi86bridge.c.

DP_BRIDGE_14

#define DP_BRIDGE_14   0x03

Definition at line 25 of file sn65dsi86bridge.c.

DP_BRIDGE_CONFIGURATION_SET

#define DP_BRIDGE_CONFIGURATION_SET   0x10a

Definition at line 26 of file sn65dsi86bridge.c.

DP_BRIDGE_DPCD_REV

#define DP_BRIDGE_DPCD_REV   0x700

Definition at line 21 of file sn65dsi86bridge.c.

DP_CLK_FUDGE_DEN

#define DP_CLK_FUDGE_DEN   8

Definition at line 18 of file sn65dsi86bridge.c.

DP_CLK_FUDGE_NUM

#define DP_CLK_FUDGE_NUM   10

Definition at line 17 of file sn65dsi86bridge.c.

DP_LANE_COUNT_MASK

#define DP_LANE_COUNT_MASK   0xf

Definition at line 32 of file sn65dsi86bridge.c.

DP_LINK_BW_1_62

#define DP_LINK_BW_1_62   0x06

Definition at line 36 of file sn65dsi86bridge.c.

DP_LINK_BW_2_7

#define DP_LINK_BW_2_7   0x0a

Definition at line 37 of file sn65dsi86bridge.c.

DP_LINK_BW_5_4

#define DP_LINK_BW_5_4   0x14

Definition at line 38 of file sn65dsi86bridge.c.

DP_LINK_BW_SET

#define DP_LINK_BW_SET   0x100

Definition at line 35 of file sn65dsi86bridge.c.

DP_MAX_LANE_COUNT

#define DP_MAX_LANE_COUNT   0x002

Definition at line 28 of file sn65dsi86bridge.c.

DP_MAX_LINK_RATE [1/2]

#define DP_MAX_LINK_RATE   0x001

Definition at line 30 of file sn65dsi86bridge.c.

DP_MAX_LINK_RATE [2/2]

#define DP_MAX_LINK_RATE   0x001

Definition at line 30 of file sn65dsi86bridge.c.

DP_MAX_SUPPORTED_RATES

#define DP_MAX_SUPPORTED_RATES   8 /* 16-bit little-endian */

Definition at line 31 of file sn65dsi86bridge.c.

DP_SUPPORTED_LINK_RATES

#define DP_SUPPORTED_LINK_RATES   0x010 /* eDP 1.4 */

Definition at line 29 of file sn65dsi86bridge.c.

MAX_DSI_CLK_FREQ_MHZ

#define MAX_DSI_CLK_FREQ_MHZ   750

Definition at line 42 of file sn65dsi86bridge.c.

MIN_DSI_CLK_FREQ_MHZ

#define MIN_DSI_CLK_FREQ_MHZ   40

Definition at line 41 of file sn65dsi86bridge.c.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
HPD_ENABLE
HPD_DISABLE

Definition at line 109 of file sn65dsi86bridge.c.

anonymous enum

anonymous enum

Enumerator
SOT_ERR_TOL_DSI
CHB_DSI_LANES
CHA_DSI_LANES
DSI_CHANNEL_MODE
LEFT_RIGHT_PIXELS

Definition at line 114 of file sn65dsi86bridge.c.

aux_cmd_status

enum aux_cmd_status

Enumerator
NAT_I2C_FAIL
AUX_SHORT
AUX_DFER
AUX_RPLY_TOUT
SEND_INT

Definition at line 127 of file sn65dsi86bridge.c.

bridge_regs

enum bridge_regs

Enumerator
SN_DPPLL_SRC_REG
SN_PLL_ENABLE_REG
SN_DSI_LANES_REG
SN_DSIA_CLK_FREQ_REG
SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG
SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG
SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG
SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG
SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG
SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG
SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG
SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG
SN_CHA_HORIZONTAL_BACK_PORCH_REG
SN_CHA_VERTICAL_BACK_PORCH_REG
SN_CHA_HORIZONTAL_FRONT_PORCH_REG
SN_CHA_VERTICAL_FRONT_PORCH_REG
SN_COLOR_BAR_REG
SN_ENH_FRAME_REG
SN_DATA_FORMAT_REG
SN_HPD_DISABLE_REG
SN_I2C_CLAIM_ADDR_EN1
SN_AUX_WDATA_REG_0
SN_AUX_WDATA_REG_1
SN_AUX_WDATA_REG_2
SN_AUX_WDATA_REG_3
SN_AUX_WDATA_REG_4
SN_AUX_WDATA_REG_5
SN_AUX_WDATA_REG_6
SN_AUX_WDATA_REG_7
SN_AUX_WDATA_REG_8
SN_AUX_WDATA_REG_9
SN_AUX_WDATA_REG_10
SN_AUX_WDATA_REG_11
SN_AUX_WDATA_REG_12
SN_AUX_WDATA_REG_13
SN_AUX_WDATA_REG_14
SN_AUX_WDATA_REG_15
SN_AUX_ADDR_19_16_REG
SN_AUX_ADDR_15_8_REG
SN_AUX_ADDR_7_0_REG
SN_AUX_LENGTH_REG
SN_AUX_CMD_REG
SN_AUX_RDATA_REG_0
SN_AUX_RDATA_REG_1
SN_AUX_RDATA_REG_2
SN_AUX_RDATA_REG_3
SN_AUX_RDATA_REG_4
SN_AUX_RDATA_REG_5
SN_AUX_RDATA_REG_6
SN_AUX_RDATA_REG_7
SN_AUX_RDATA_REG_8
SN_AUX_RDATA_REG_9
SN_AUX_RDATA_REG_10
SN_AUX_RDATA_REG_11
SN_AUX_RDATA_REG_12
SN_AUX_RDATA_REG_13
SN_AUX_RDATA_REG_14
SN_AUX_RDATA_REG_15
SN_SSC_CONFIG_REG
SN_DATARATE_CONFIG_REG
SN_ML_TX_MODE_REG
SN_AUX_CMD_STATUS_REG

Definition at line 44 of file sn65dsi86bridge.c.

ml_tx_mode

enum ml_tx_mode

Enumerator
MAIN_LINK_OFF
NORMAL_MODE
TPS1
TPS2
TPS3
PRBS7
HBR2_COMPLIANCE_EYE_PATTERN
SYMBOL_ERR_RATE_MEASUREMENT_PATTERN
CUTSOM_PATTERN
FAST_LINK_TRAINING
SEMI_AUTO_LINK_TRAINING
REDRIVER_SEMI_AUTO_LINK_TRAINING

Definition at line 135 of file sn65dsi86bridge.c.

vstream_config

enum vstream_config

Enumerator
VSTREAM_DISABLE
VSTREAM_ENABLE

Definition at line 122 of file sn65dsi86bridge.c.

Function Documentation

sn65dsi86_backlight_enable()

void sn65dsi86_backlight_enable	(	uint8_t	bus,
		uint8_t	chip
	)

Definition at line 439 of file sn65dsi86bridge.c.

References chip, DP_BACKLIGHT_BRIGHTNESS_MSB, DP_BACKLIGHT_CONTROL_MODE_DPCD, DP_BACKLIGHT_ENABLE, DP_BACKLIGHT_MODE_SET, DP_DISPLAY_CONTROL_REGISTER, DPCD_WRITE, sn65dsi86_bridge_aux_request(), and val.

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sn65dsi86_bridge_assr_config()

static void sn65dsi86_bridge_assr_config ( uint8_t  bus, uint8_t  chip, int  enable  )

static

Definition at line 453 of file sn65dsi86bridge.c.

References chip, i2c_write_field(), SN_ENH_FRAME_REG, VSTREAM_DISABLE, and VSTREAM_ENABLE.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_aux_request()

static enum cb_err sn65dsi86_bridge_aux_request ( uint8_t  bus, uint8_t  chip, unsigned int  target_reg, unsigned int  total_size, enum aux_request  request, uint8_t *  data  )

static

Definition at line 154 of file sn65dsi86bridge.c.

Referenced by sn65dsi86_backlight_enable(), sn65dsi86_bridge_dp_lane_config(), sn65dsi86_bridge_link_training(), and sn65dsi86_bridge_valid_dp_rates().

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sn65dsi86_bridge_configure()

void sn65dsi86_bridge_configure	(	uint8_t	bus,
		uint8_t	chip,
		struct edid *	edid,
		uint32_t	num_of_lanes,
		uint32_t	dsi_bpp
	)

Definition at line 481 of file sn65dsi86bridge.c.

References chip, i2c_write_field(), i2c_writeb(), sn65dsi86_bridge_assr_config(), sn65dsi86_bridge_dp_lane_config(), sn65dsi86_bridge_link_training(), sn65dsi86_bridge_set_bridge_active_timing(), sn65dsi86_bridge_set_dp_clock_range(), sn65dsi86_bridge_set_dsi_clock_range(), SN_COLOR_BAR_REG, SN_DATA_FORMAT_REG, and SN_DSI_LANES_REG.

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sn65dsi86_bridge_dp_lane_config()

static int sn65dsi86_bridge_dp_lane_config ( uint8_t  bus, uint8_t  chip  )

static

Definition at line 461 of file sn65dsi86bridge.c.

References chip, DP_LANE_COUNT_MASK, DP_MAX_LANE_COUNT, DPCD_READ, i2c_write_field(), MIN, sn65dsi86_bridge_aux_request(), and SN_SSC_CONFIG_REG.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_init()

void sn65dsi86_bridge_init	(	uint8_t	bus,
		uint8_t	chip,
		enum dp_pll_clk_src	ref_clk
	)

Definition at line 472 of file sn65dsi86bridge.c.

References chip, HPD_DISABLE, i2c_write_field(), SN_DPPLL_SRC_REG, and SN_HPD_DISABLE_REG.

Referenced by display_startup().

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sn65dsi86_bridge_link_training()

static void sn65dsi86_bridge_link_training ( uint8_t  bus, uint8_t  chip  )

static

Definition at line 400 of file sn65dsi86bridge.c.

References BIOS_ERR, BIT, buf, chip, DP_BRIDGE_CONFIGURATION_SET, DPCD_WRITE, i2c_readb(), i2c_writeb(), MAIN_LINK_OFF, NORMAL_MODE, printk, SEMI_AUTO_LINK_TRAINING, sn65dsi86_bridge_aux_request(), SN_DPPLL_SRC_REG, SN_ML_TX_MODE_REG, SN_PLL_ENABLE_REG, and wait_ms.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_read_edid()

enum cb_err sn65dsi86_bridge_read_edid	(	uint8_t	bus,
		uint8_t	chip,
		struct edid *	out
	)

Definition at line 154 of file sn65dsi86bridge.c.

Referenced by display_startup().

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sn65dsi86_bridge_set_bridge_active_timing()

static void sn65dsi86_bridge_set_bridge_active_timing ( uint8_t  bus, uint8_t  chip, struct edid *  edid  )

static

Definition at line 370 of file sn65dsi86bridge.c.

References BRIDGE_GETHIGHERBYTE, BRIDGE_GETLOWERBYTE, chip, edid_mode::ha, edid_mode::hbl, edid_mode::hso, edid_mode::hspw, i2c_writeb(), edid::mode, SN_CHA_ACTIVE_LINE_LENGTH_HIGH_REG, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, SN_CHA_HORIZONTAL_BACK_PORCH_REG, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, SN_CHA_VERTICAL_BACK_PORCH_REG, SN_CHA_VERTICAL_DISPLAY_SIZE_HIGH_REG, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, SN_CHA_VERTICAL_FRONT_PORCH_REG, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, edid_mode::va, edid_mode::vbl, edid_mode::vso, and edid_mode::vspw.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_set_dp_clock_range()

static void sn65dsi86_bridge_set_dp_clock_range ( uint8_t  bus, uint8_t  chip, struct edid *  edid, uint32_t  num_of_lanes  )

static

Definition at line 337 of file sn65dsi86bridge.c.

References ARRAY_SIZE, BIOS_ERR, chip, DIV_ROUND_UP, DP_CLK_FUDGE_DEN, DP_CLK_FUDGE_NUM, i2c_write_field(), KHz, edid::mode, edid_mode::pixel_clock, printk, sn65dsi86_bridge_dp_rate_lut, sn65dsi86_bridge_valid_dp_rates(), and SN_DATARATE_CONFIG_REG.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_set_dsi_clock_range()

static void sn65dsi86_bridge_set_dsi_clock_range ( uint8_t  bus, uint8_t  chip, struct edid *  edid, uint32_t  num_of_lanes, uint32_t  bpp  )

static

Definition at line 317 of file sn65dsi86bridge.c.

References chip, i2c_writeb(), KHz, MAX, MAX_DSI_CLK_FREQ_MHZ, MHz, MIN, MIN_DSI_CLK_FREQ_MHZ, edid::mode, edid_mode::pixel_clock, and SN_DSIA_CLK_FREQ_REG.

Referenced by sn65dsi86_bridge_configure().

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sn65dsi86_bridge_valid_dp_rates()

static void sn65dsi86_bridge_valid_dp_rates ( uint8_t  bus, uint8_t  chip, bool  rate_valid[]  )

static

Definition at line 259 of file sn65dsi86bridge.c.

References __fallthrough, ARRAY_SIZE, BIOS_ERR, chip, DP_BRIDGE_14, DP_BRIDGE_DPCD_REV, DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4, DP_MAX_LINK_RATE, DP_MAX_SUPPORTED_RATES, DP_SUPPORTED_LINK_RATES, DPCD_READ, KHz, MHz, printk, sn65dsi86_bridge_aux_request(), and sn65dsi86_bridge_dp_rate_lut.

Referenced by sn65dsi86_bridge_set_dp_clock_range().

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Variable Documentation

sn65dsi86_bridge_dp_rate_lut

const unsigned int sn65dsi86_bridge_dp_rate_lut[]

static

Initial value:

= {
        0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
}

Definition at line 154 of file sn65dsi86bridge.c.

Referenced by sn65dsi86_bridge_set_dp_clock_range(), and sn65dsi86_bridge_valid_dp_rates().