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| #define | IC_CON offsetof(I2C_REGS, ic_con) |
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| #define | IC_TAR offsetof(I2C_REGS, ic_tar) |
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| #define | IC_DATA_CMD offsetof(I2C_REGS, ic_data_cmd) |
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| #define | IC_SS_SCL_HCNT offsetof(I2C_REGS, ic_ss_scl_hcnt) |
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| #define | IC_SS_SCL_LCNT offsetof(I2C_REGS, ic_ss_scl_lcnt) |
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| #define | IC_FS_SCL_HCNT offsetof(I2C_REGS, ic_fs_scl_hcnt) |
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| #define | IC_FS_SCL_LCNT offsetof(I2C_REGS, ic_fs_scl_lcnt) |
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| #define | IC_INTR_STAT offsetof(I2C_REGS, ic_intr_stat) |
| |
| #define | IC_INTR_MASK offsetof(I2C_REGS, ic_intr_mask) |
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| #define | IC_RAW_INTR_STAT offsetof(I2C_REGS, ic_raw_intr_stat) |
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| #define | IC_RX_TL offsetof(I2C_REGS, ic_rx_tl) |
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| #define | IC_TX_TL offsetof(I2C_REGS, ic_tx_tl) |
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| #define | IC_CLR_INTR offsetof(I2C_REGS, ic_clr_intr) |
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| #define | IC_CLR_RX_UNDER offsetof(I2C_REGS, ic_clr_rx_under) |
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| #define | IC_CLR_RX_OVER offsetof(I2C_REGS, ic_clr_rx_over) |
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| #define | IC_CLR_TX_OVER offsetof(I2C_REGS, ic_clr_tx_over) |
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| #define | IC_CLR_RD_REQ offsetof(I2C_REGS, ic_clr_rd_req) |
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| #define | IC_CLR_TX_ABRT offsetof(I2C_REGS, ic_clr_tx_abrt) |
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| #define | IC_CLR_ACTIVITY offsetof(I2C_REGS, ic_clr_activity) |
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| #define | IC_CLR_STOP_DET offsetof(I2C_REGS, ic_clr_stop_det) |
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| #define | IC_CLR_START_DET offsetof(I2C_REGS, ic_clr_start_det) |
| |
| #define | IC_ENABLE offsetof(I2C_REGS, ic_enable) |
| |
| #define | IC_STATUS offsetof(I2C_REGS, ic_status) |
| |
| #define | IC_TXFLR offsetof(I2C_REGS, ic_txflr) |
| |
| #define | IC_RXFLR offsetof(I2C_REGS, ic_rxflr) |
| |
| #define | IC_SDA_HOLD offsetof(I2C_REGS, ic_sda_hold) |
| |
| #define | IC_TX_ABRT_SOURCE offsetof(I2C_REGS, ic_tx_abrt_source) |
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| #define | IC_ENABLE_STATUS offsetof(I2C_REGS, ic_enable_status) |
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| #define | IC_FS_SPKLEN offsetof(I2C_REGS, ic_fs_spklen) |
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| #define | IC_CON_RESTART_EN 0x00000020 /* Enable start/restart */ |
| |
| #define | IC_CON_10B 0x00000010 /* 10-bit addressing */ |
| |
| #define | IC_CON_7B 0 /* 7-bit addressing */ |
| |
| #define | IC_CON_SPEED 0x00000006 /* I2C bus speed */ |
| |
| #define | IC_CON_SPEED_400_KHz 0x00000004 /* Fast mode */ |
| |
| #define | IC_CON_SPEED_100_KHz 0x00000002 /* Standard mode */ |
| |
| #define | IC_CON_MASTER_MODE 0x00000001 /* Enable master mode */ |
| |
| #define | IC_DATA_CMD_RESTART 0x00000400 /* Send restart before byte */ |
| |
| #define | IC_DATA_CMD_STOP 0x00000200 /* Send stop after byte */ |
| |
| #define | IC_DATA_CMD_CMD 0x00000100 /* Type of transaction */ |
| |
| #define | IC_DATA_CMD_READ IC_DATA_CMD_CMD |
| |
| #define | IC_DATA_CMD_WRITE 0 |
| |
| #define | IC_DATA_CMD_DATA 0x000000ff /* Data byte */ |
| |
| #define | IC_INTR_START_DET 0x00000400 /* Start bit detected */ |
| |
| #define | IC_INTR_STOP_DET 0x00000200 /* Stop bit detected */ |
| |
| #define | IC_INTR_ACTIVITY 0x00000100 /* Activity detected */ |
| |
| #define | IC_INTR_TX_ABRT 0x00000040 /* Transmit abort */ |
| |
| #define | IC_INTR_RD_REQ 0x00000020 /* Read request */ |
| |
| #define | IC_INTR_TX_EMPTY 0x00000010 /* TX FIFO is empty */ |
| |
| #define | IC_INTR_TX_OVER 0x00000008 /* TX FIFO overflow */ |
| |
| #define | IC_INTR_RX_FULL 0x00000004 /* Receive FIFO is full */ |
| |
| #define | IC_INTR_RX_OVER 0x00000002 /* Receive FIFO overflow */ |
| |
| #define | IC_INTR_RX_UNDER 0x00000001 /* Receive FIFO underflow */ |
| |
| #define | IC_ENABLE_CONTROLLER 0x00000001 /* Enable the I2C controller */ |
| |
| #define | IC_STATUS_MST_ACTIVITY 0x00000020 /* Master FSM activity */ |
| |
| #define | IC_STATUS_RFF 0x00000010 /* Receive FIFO completely full */ |
| |
| #define | IC_STATUS_RFNE 0x00000008 /* Receive FIFO not empty */ |
| |
| #define | IC_STATUS_TFE 0x00000004 /* Transmit FIFO completely empty */ |
| |
| #define | IC_STATUS_TFNF 0x00000002 /* Transmit FIFO not full */ |
| |
| #define | IC_STATUS_ACTIVITY 0x00000001 /* Activity */ |
| |
1.9.1