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dramc_soc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
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#define __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__
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typedef
enum
{
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CHANNEL_A
= 0,
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CHANNEL_B
,
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CHANNEL_C
,
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CHANNEL_D
,
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CHANNEL_MAX
,
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}
DRAM_CHANNEL_T
;
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typedef
enum
{
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RANK_0
= 0,
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RANK_1
,
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RANK_MAX
,
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}
DRAM_RANK_T
;
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/* DRAM SHUFFLE register type */
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typedef
enum
{
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DRAM_DFS_SHUFFLE_1
= 0,
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DRAM_DFS_SHUFFLE_2
,
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DRAM_DFS_SHUFFLE_3
,
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DRAM_DFS_SHUFFLE_4
,
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DRAM_DFS_SHUFFLE_5
,
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DRAM_DFS_SHUFFLE_6
,
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DRAM_DFS_SHUFFLE_7
,
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DRAM_DFS_SHUFFLE_MAX
,
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}
DRAM_DFS_SHUFFLE_TYPE_T
;
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/*
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* Internal CBT mode enum
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* 1. Calibration flow uses vGet_Dram_CBT_Mode to
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* differentiate between mixed vs non-mixed LP4
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* 2. Declared as dram_cbt_mode[RANK_MAX] internally to
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* store each rank's CBT mode type
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*/
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typedef
enum
{
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CBT_NORMAL_MODE
= 0,
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CBT_BYTE_MODE1
,
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}
DRAM_CBT_MODE_T
;
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#define DRAM_DFS_SHU_MAX DRAM_DFS_SHUFFLE_MAX
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#define DQS_NUMBER_LP4 2
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#define DQS_BIT_NUMBER 8
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#define DQ_DATA_WIDTH_LP4 16
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#endif
/* __SOC_MEDIATEK_MT8195_DRAMC_SOC_H__ */
CHANNEL_A
@ CHANNEL_A
Definition:
dramc_soc.h:7
CHANNEL_B
@ CHANNEL_B
Definition:
dramc_soc.h:8
DRAM_RANK_T
DRAM_RANK_T
Definition:
dramc_soc.h:12
RANK_1
@ RANK_1
Definition:
dramc_soc.h:14
RANK_0
@ RANK_0
Definition:
dramc_soc.h:13
RANK_MAX
@ RANK_MAX
Definition:
dramc_soc.h:15
DRAM_CBT_MODE_T
DRAM_CBT_MODE_T
Definition:
dramc_soc.h:45
CBT_BYTE_MODE1
@ CBT_BYTE_MODE1
Definition:
dramc_soc.h:47
CBT_NORMAL_MODE
@ CBT_NORMAL_MODE
Definition:
dramc_soc.h:46
DRAM_DFS_SHUFFLE_TYPE_T
DRAM_DFS_SHUFFLE_TYPE_T
Definition:
dramc_soc.h:24
DRAM_DFS_SHUFFLE_MAX
@ DRAM_DFS_SHUFFLE_MAX
Definition:
dramc_soc.h:35
DRAM_DFS_SHUFFLE_6
@ DRAM_DFS_SHUFFLE_6
Definition:
dramc_soc.h:30
DRAM_DFS_SHUFFLE_1
@ DRAM_DFS_SHUFFLE_1
Definition:
dramc_soc.h:25
DRAM_DFS_SHUFFLE_3
@ DRAM_DFS_SHUFFLE_3
Definition:
dramc_soc.h:27
DRAM_DFS_SHUFFLE_5
@ DRAM_DFS_SHUFFLE_5
Definition:
dramc_soc.h:29
DRAM_DFS_SHUFFLE_7
@ DRAM_DFS_SHUFFLE_7
Definition:
dramc_soc.h:31
DRAM_DFS_SHUFFLE_4
@ DRAM_DFS_SHUFFLE_4
Definition:
dramc_soc.h:28
DRAM_DFS_SHUFFLE_2
@ DRAM_DFS_SHUFFLE_2
Definition:
dramc_soc.h:26
DRAM_CHANNEL_T
DRAM_CHANNEL_T
Definition:
dramc_soc.h:6
CHANNEL_MAX
@ CHANNEL_MAX
Definition:
dramc_soc.h:9
CHANNEL_C
@ CHANNEL_C
Definition:
dramc_soc.h:9
CHANNEL_D
@ CHANNEL_D
Definition:
dramc_soc.h:10
src
soc
mediatek
mt8195
include
soc
dramc_soc.h
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