coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smn.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
amdblocks/smn.h
>
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#include <
device/pci_ops.h
>
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#include <soc/pci_devs.h>
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#include <types.h>
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/* SMN registers accessed indirectly using an index/data pair in D0F00 config space */
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#define SMN_INDEX_ADDR 0xb8
/* 32 bit */
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#define SMN_DATA_ADDR 0xbc
/* 32 bit */
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uint32_t
smn_read32
(
uint32_t
reg)
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{
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pci_write_config32
(
SOC_GNB_DEV
,
SMN_INDEX_ADDR
, reg);
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return
pci_read_config32
(
SOC_GNB_DEV
,
SMN_DATA_ADDR
);
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}
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void
smn_write32
(
uint32_t
reg,
uint32_t
val
)
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{
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pci_write_config32
(
SOC_GNB_DEV
,
SMN_INDEX_ADDR
, reg);
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pci_write_config32
(
SOC_GNB_DEV
,
SMN_DATA_ADDR
,
val
);
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}
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
pci_read_config32
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition:
pci_ops.h:58
SMN_DATA_ADDR
#define SMN_DATA_ADDR
Definition:
smn.c:10
smn_read32
uint32_t smn_read32(uint32_t reg)
Definition:
smn.c:12
smn_write32
void smn_write32(uint32_t reg, uint32_t val)
Definition:
smn.c:18
SMN_INDEX_ADDR
#define SMN_INDEX_ADDR
Definition:
smn.c:9
smn.h
SOC_GNB_DEV
#define SOC_GNB_DEV
Definition:
pci_devs.h:13
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
val
u8 val
Definition:
sys.c:300
src
soc
amd
common
block
smn
smn.c
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