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◆ ACPI_BASE_ADDRESS
#define ACPI_BASE_ADDRESS 0x400 |
◆ ACPI_BASE_SIZE
#define ACPI_BASE_SIZE 0x100 |
◆ ACPI_PMIO_CST_REG
◆ EARLY_GSPI_BASE_ADDRESS
#define EARLY_GSPI_BASE_ADDRESS 0xfe011000 |
◆ EARLY_I2C_BASE
◆ EARLY_I2C_BASE_ADDRESS
#define EARLY_I2C_BASE_ADDRESS 0xfe020000 |
◆ HECI1_BASE_ADDRESS
#define HECI1_BASE_ADDRESS 0xfed1a000 |
◆ MCH_BASE_ADDRESS
#define MCH_BASE_ADDRESS 0xfed10000 |
◆ MCH_BASE_SIZE
#define MCH_BASE_SIZE (32 * KiB) |
◆ P2SB_BAR
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS |
◆ P2SB_SIZE
#define P2SB_SIZE (16 * MiB) |
◆ PCH_PWRM_BASE_ADDRESS
#define PCH_PWRM_BASE_ADDRESS 0xfe042000 |
◆ PMC_BAR0_SIZE
#define PMC_BAR0_SIZE (8 * KiB) |
◆ PMC_BAR1
#define PMC_BAR1 0xfe044000 |
◆ PMG_IO_BASE_CST_RNG_BLK_SIZE
#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 |
◆ PSF3_BASE_ADDRESS
#define PSF3_BASE_ADDRESS 0x1e00 |
◆ R_ACPI_PM1_TMR
#define R_ACPI_PM1_TMR 0x8 |
◆ SPI_BASE_ADDRESS
#define SPI_BASE_ADDRESS 0xfe010000 |
◆ SRAM_BASE_0
#define SRAM_BASE_0 0xfe900000 |
◆ SRAM_BASE_2
#define SRAM_BASE_2 0xfe902000 |
◆ SRAM_SIZE_0
#define SRAM_SIZE_0 (8 * KiB) |
◆ SRAM_SIZE_2
#define SRAM_SIZE_2 (4 * KiB) |
◆ TCO_BASE_ADDRESS
◆ TCO_BASE_SIZE
#define TCO_BASE_SIZE 0x20 |