#include <chip.h>

Collaboration diagram for southbridge_intel_i82801jx_config:

Data Fields
uint8_t	gpi0_routing
	GPI Routing configuration. More...

uint8_t	gpi1_routing

uint8_t	gpi2_routing

uint8_t	gpi3_routing

uint8_t	gpi4_routing

uint8_t	gpi5_routing

uint8_t	gpi6_routing

uint8_t	gpi7_routing

uint8_t	gpi8_routing

uint8_t	gpi9_routing

uint8_t	gpi10_routing

uint8_t	gpi11_routing

uint8_t	gpi12_routing

uint8_t	gpi13_routing

uint8_t	gpi14_routing

uint8_t	gpi15_routing

uint32_t	gpe0_en

uint16_t	alt_gp_smi_en

uint8_t	sata_port_map: 6

unsigned int	sata_clock_request: 1

unsigned int	c4onc3_enable:1

unsigned int	c5_enable: 1

unsigned int	c6_enable: 1

unsigned int	throttle_duty: 3

unsigned int	pcie_slot_implemented: 6

struct {
uint8_t value: 8

uint8_t scale: 2

}	pcie_power_limits [6]

uint8_t	pcie_hotplug_map [8]

uint32_t	gen1_dec

uint32_t	gen2_dec

uint32_t	gen3_dec

uint32_t	gen4_dec

Detailed Description

Definition at line 13 of file chip.h.

Field Documentation

◆ alt_gp_smi_en

uint16_t southbridge_intel_i82801jx_config::alt_gp_smi_en

Definition at line 41 of file chip.h.

◆ c4onc3_enable

unsigned int southbridge_intel_i82801jx_config::c4onc3_enable

Definition at line 47 of file chip.h.

◆ c5_enable

unsigned int southbridge_intel_i82801jx_config::c5_enable

Definition at line 48 of file chip.h.

◆ c6_enable

unsigned int southbridge_intel_i82801jx_config::c6_enable

Definition at line 49 of file chip.h.

◆ gen1_dec

uint32_t southbridge_intel_i82801jx_config::gen1_dec

Definition at line 65 of file chip.h.

◆ gen2_dec

uint32_t southbridge_intel_i82801jx_config::gen2_dec

Definition at line 66 of file chip.h.

◆ gen3_dec

uint32_t southbridge_intel_i82801jx_config::gen3_dec

Definition at line 67 of file chip.h.

◆ gen4_dec

uint32_t southbridge_intel_i82801jx_config::gen4_dec

Definition at line 68 of file chip.h.

◆ gpe0_en

uint32_t southbridge_intel_i82801jx_config::gpe0_en

Definition at line 40 of file chip.h.

◆ gpi0_routing

uint8_t southbridge_intel_i82801jx_config::gpi0_routing

GPI Routing configuration.

Only the lower two bits have a meaning: 00: No effect 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10: SCI (if corresponding GPIO_EN bit is also set) 11: reserved

Definition at line 23 of file chip.h.

◆ gpi10_routing

uint8_t southbridge_intel_i82801jx_config::gpi10_routing

Definition at line 33 of file chip.h.

◆ gpi11_routing

uint8_t southbridge_intel_i82801jx_config::gpi11_routing

Definition at line 34 of file chip.h.

◆ gpi12_routing

uint8_t southbridge_intel_i82801jx_config::gpi12_routing

Definition at line 35 of file chip.h.

◆ gpi13_routing

uint8_t southbridge_intel_i82801jx_config::gpi13_routing

Definition at line 36 of file chip.h.

◆ gpi14_routing

uint8_t southbridge_intel_i82801jx_config::gpi14_routing

Definition at line 37 of file chip.h.

◆ gpi15_routing

uint8_t southbridge_intel_i82801jx_config::gpi15_routing

Definition at line 38 of file chip.h.

◆ gpi1_routing

uint8_t southbridge_intel_i82801jx_config::gpi1_routing

Definition at line 24 of file chip.h.

◆ gpi2_routing

uint8_t southbridge_intel_i82801jx_config::gpi2_routing

Definition at line 25 of file chip.h.

◆ gpi3_routing

uint8_t southbridge_intel_i82801jx_config::gpi3_routing

Definition at line 26 of file chip.h.

◆ gpi4_routing

uint8_t southbridge_intel_i82801jx_config::gpi4_routing

Definition at line 27 of file chip.h.

◆ gpi5_routing

uint8_t southbridge_intel_i82801jx_config::gpi5_routing

Definition at line 28 of file chip.h.

◆ gpi6_routing

uint8_t southbridge_intel_i82801jx_config::gpi6_routing

Definition at line 29 of file chip.h.

◆ gpi7_routing

uint8_t southbridge_intel_i82801jx_config::gpi7_routing

Definition at line 30 of file chip.h.

◆ gpi8_routing

uint8_t southbridge_intel_i82801jx_config::gpi8_routing

Definition at line 31 of file chip.h.

◆ gpi9_routing

uint8_t southbridge_intel_i82801jx_config::gpi9_routing

Definition at line 32 of file chip.h.

◆ pcie_hotplug_map

uint8_t southbridge_intel_i82801jx_config::pcie_hotplug_map[8]

Definition at line 62 of file chip.h.

◆

struct { ... } southbridge_intel_i82801jx_config::pcie_power_limits[6]

◆ pcie_slot_implemented

unsigned int southbridge_intel_i82801jx_config::pcie_slot_implemented

Definition at line 54 of file chip.h.

◆ sata_clock_request

unsigned int southbridge_intel_i82801jx_config::sata_clock_request

Definition at line 45 of file chip.h.

◆ sata_port_map

uint8_t southbridge_intel_i82801jx_config::sata_port_map

Definition at line 44 of file chip.h.

◆ scale

uint8_t southbridge_intel_i82801jx_config::scale

Definition at line 59 of file chip.h.

◆ throttle_duty

unsigned int southbridge_intel_i82801jx_config::throttle_duty

Definition at line 51 of file chip.h.

◆ value

uint8_t southbridge_intel_i82801jx_config::value

Definition at line 58 of file chip.h.

The documentation for this struct was generated from the following file:

src/southbridge/intel/i82801jx/chip.h

Data Fields