![]() |
coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
|
#include <device/pnp_type.h>
Go to the source code of this file.
Macros | |
#define | LPC47N227_PP 1 /* Parallel Port */ |
#define | LPC47N227_SP1 2 /* COM1 */ |
#define | LPC47N227_SP2 3 /* COM2 */ |
#define | LPC47N227_KBDC 5 /* Keyboard */ |
#define | LPC47N227_MAX_CONFIG_REGISTER 0x39 |
Functions | |
void | pnp_enter_conf_state (pnp_devfn_t dev) |
void | pnp_exit_conf_state (pnp_devfn_t dev) |
void | lpc47n227_enable_serial (pnp_devfn_t dev, u16 iobase) |
Configure the base I/O port of the specified serial device and enable the serial device. More... | |
#define LPC47N227_KBDC 5 /* Keyboard */ |
Definition at line 16 of file lpc47n227.h.
#define LPC47N227_MAX_CONFIG_REGISTER 0x39 |
Definition at line 18 of file lpc47n227.h.
#define LPC47N227_PP 1 /* Parallel Port */ |
Definition at line 13 of file lpc47n227.h.
#define LPC47N227_SP1 2 /* COM1 */ |
Definition at line 14 of file lpc47n227.h.
#define LPC47N227_SP2 3 /* COM2 */ |
Definition at line 15 of file lpc47n227.h.
void lpc47n227_enable_serial | ( | pnp_devfn_t | dev, |
u16 | iobase | ||
) |
Configure the base I/O port of the specified serial device and enable the serial device.
dev | High 8 bits = Super I/O port, low 8 bits = logical device number. |
iobase | Processor I/O port address to assign to this serial device. |
Definition at line 99 of file early_serial.c.
References lpc47n227_pnp_set_enable(), lpc47n227_pnp_set_iobase(), pnp_enter_conf_state(), and pnp_exit_conf_state().
Referenced by bootblock_mainboard_early_init().
void pnp_enter_conf_state | ( | pnp_devfn_t | dev | ) |
Definition at line 30 of file early_serial.c.
void pnp_exit_conf_state | ( | pnp_devfn_t | dev | ) |
Definition at line 38 of file early_serial.c.