13 #ifndef __P6_L2_CACHE_H
14 #define __P6_L2_CACHE_H
18 #define EBL_CR_POWERON 0x2A
20 #define BBL_CR_D0 0x88
21 #define BBL_CR_D1 0x89
22 #define BBL_CR_D2 0x8A
23 #define BBL_CR_D3 0x8B
25 #define BBL_CR_ADDR 0x116
26 #define BBL_CR_DECC 0x118
27 #define BBL_CR_CTL 0x119
28 #define BBL_CR_TRIG 0x11A
29 #define BBL_CR_BUSY 0x11B
30 #define BBL_CR_CTL3 0x11E
32 #define BBLCR3_L2_CONFIGURED (1<<0)
34 #define BBLCR3_L2_LATENCY 0x1e
35 #define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5)
36 #define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6)
37 #define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7)
38 #define BBLCR3_L2_ENABLED (1<<8)
40 #define BBLCR3_L2_SIZE (0x1f << 13)
41 #define BBLCR3_L2_SIZE_256K (0x01 << 13)
42 #define BBLCR3_L2_SIZE_512K (0x02 << 13)
43 #define BBLCR3_L2_SIZE_1M (0x04 << 13)
44 #define BBLCR3_L2_SIZE_2M (0x08 << 13)
45 #define BBLCR3_L2_SIZE_4M (0x10 << 13)
47 #define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20);
51 #define BBLCR3_L2_SUPPLIED_ECC 0x40000
53 #define BBLCR3_L2_HARDWARE_DISABLE (1<<23)
55 #define BBLCR3_L2_NOT_PRESENT (1<<23)
58 #define L2CMD_RLU 0x0c
59 #define L2CMD_TRR 0x0e
63 #define L2CMD_TWR 0x08
64 #define L2CMD_TWW 0x1c
67 #define L2CMD_MESI_M 3
68 #define L2CMD_MESI_E 2
69 #define L2CMD_MESI_S 1
70 #define L2CMD_MESI_I 0
int calculate_l2_latency(void)
int calculate_l2_physical_address_range(void)
int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command)
int p6_configure_l2_cache(void)
int write_l2(u32 address, u32 data)
int calculate_l2_cache_size(void)
int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low)