70 {0x10, 0x02}, {0x50, 0x02}, {0x20, 0x04}, {0x60, 0x06},
71 {0x00, 0x08}, {0x40, 0x0C}, {0x12, 0x06}, {0x52, 0x0A},
72 {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0xFF, 0x00}
76 {0x12, 0x14}, {0x52, 0x16}, {0x22, 0x16}, {0x62, 0x16},
81 {0x60, 0x06}, {0x00, 0x08}, {0x12, 0x06}, {0x52, 0x0A},
82 {0x22, 0x0E}, {0x62, 0x10}, {0x02, 0x10}, {0x42, 0x02},
83 {0x11, 0x0E}, {0x51, 0x0C}, {0x21, 0x02}, {0x61, 0x10},
84 {0x01, 0x10}, {0x41, 0x02}, {0xFF, 0x00}
88 {0x22, 0x18}, {0x62, 0x18}, {0x02, 0x1A}, {0x11, 0x18},
93 {0x22, 0x12}, {0x62, 0x14}, {0x02, 0x16}, {0x42, 0x1E},
94 {0x11, 0x12}, {0x51, 0x16}, {0x21, 0x1E}, {0x61, 0x14},
95 {0x01, 0x16}, {0x41, 0x1E}, {0xFF, 0x00}
110 u32 eax, l, signature;
121 l = (msr.
hi >> 20) & 0x1e;
159 if (signature == 0x650) {
162 }
else if (signature == 0x670) {
169 for (le = latency_table; le->
key != eax; le++) {
171 if (le->
key == 0xff) {
173 "Could not find key %02x in latency table\n",
186 msr.
lo &= 0xffffffe1;
214 msr.
lo = (msr.
lo & 0xfffffce0) | command | (way << 8);
223 for (i = 0; i < 0x100; i++) {
227 if ((msr.
lo & 1) == 0)
246 return (msr.
lo >> 0x15);
263 if ((v1 & 0x20) == 0) {
272 for (i = 0; i < v2; i++) {
283 data2 = (i << 11) & 0x1800;
302 u32 data_high,
u32 data_low)
318 if (msr.
lo != data_low || msr.
hi != data_high)
319 return (msr.
lo & 0xffff);
342 if ((v & 0x20) == 0) {
356 eax = bblcr3 | cache_setting;
522 const u32 data1 = 0xaa55aa55;
523 const u32 data2 = 0xaaaaaaaa;
570 int cache_size, bank;
574 int badclk1, badclk2, clkratio;
593 if (signature == 0x630) {
594 clkratio = 0x1c00000;
598 clkratio = 0x3c00000;
609 if (eax == badclk1 || eax == badclk2) {
627 bblctl3.
lo &= 0xff88061e;
633 bblctl3.
lo |= crctl3_or;
638 if (signature != 0x630) {
647 calc_eax = bblctl3.
lo;
658 v = (calc_eax >> 26) & 0x3;
673 bblctl3.
lo = calc_eax;
683 if (v >= 0 && (v & 0x20)) {
697 "Failed to calculate L2 physical address range");
714 cache_size = cache_size << 3;
720 bank = (bblctl3.
lo >> 11) & 0x3;
728 while (cache_size > 0) {
742 for (v = 0; v < 4; v++) {
749 "Failed on signal_l2(%x, %x)\n",
766 asm volatile (
"invd");
775 if (signature == 0x650) {
static unsigned int cpuid_eax(unsigned int op)
#define printk(level,...)
static __always_inline void enable_cache(void)
static __always_inline void disable_cache(void)
static __always_inline msr_t rdmsr(unsigned int index)
static __always_inline void wrmsr(unsigned int index, msr_t msr)
static const struct latency_entry * latency_650[]
static const struct latency_entry latency_650_t1[]
int calculate_l2_latency(void)
static const struct latency_entry latency_670_t2[]
int calculate_l2_physical_address_range(void)
int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command)
int p6_configure_l2_cache(void)
static const struct latency_entry latency_670_t1[]
int write_l2(u32 address, u32 data)
static const struct latency_entry * latency_670[]
int calculate_l2_cache_size(void)
static const struct latency_entry latency_650_t0[]
int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low)
static const struct latency_entry latency_670_t0[]
#define BBLCR3_L2_ENABLED
#define BBLCR3_L2_SIZE_4M
#define BBLCR3_L2_CRTN_PARITY_ENABLE
#define BBLCR3_L2_CONFIGURED
#define BBLCR3_L2_SUPPLIED_ECC
#define BBLCR3_L2_PHYSICAL_RANGE
#define BBLCR3_L2_ECC_CHECK_ENABLE
#define BBLCR3_L2_NOT_PRESENT
#define BBLCR3_L2_ADDR_PARITY_ENABLE
#define BBLCR3_L2_SIZE_256K
#define BBLCR3_L2_LATENCY
#define BIOS_INFO
BIOS_INFO - Expected events.
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define c(value, pmcreg, dst_bits)