mipi.h

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#ifndef __RK_MIPI_H
#define __RK_MIPI_H
 
#include <mipi/dsi.h>
#include <types.h>
 
struct rk_mipi_regs {
        u32 dsi_version;
        u32 dsi_pwr_up;
        u32 dsi_clk_cfg;
        u32 dsi_dpi_vcid;
        u32 dsi_dpi_color_coding;
        u32 dsi_dpi_cfg_pol;
        u32 dsi_dpi_lp_cmd_tim;
        u8 reserved0[0x28 - 0x18];
        u32 dsi_pckhdl_cfg;
        u8 reserved1[0x30 - 0x2c];
        u32 dsi_mode_cfg;
        u32 dsi_vid_mode_cfg;
        u32 dsi_vid_pkt_size;
        u32 dsi_vid_num_chumks;
        u32 dsi_vid_null_pkt_size;
        u32 dsi_vid_hsa_time;
        u32 dsi_vid_hbp_time;
        u32 dsi_vid_hline_time;
        u32 dsi_vid_vsa_lines;
        u32 dsi_vid_vbp_lines;
        u32 dsi_vid_vfp_lines;
        u32 dsi_vid_vactive_lines;
        u32 dsi_edpi_cmd_size;
        u32 dsi_cmd_mode_cfg;
        u32 dsi_gen_hdr;
        u32 dsi_gen_pld_data;
        u32 dsi_cmd_pkt_status;
        u32 dsi_to_cnt_cfg;
        u8 reserved2[0x88 - 0x78];
        u32 dsi_bta_to_cnt;
        u32 reserved3;
        u32 dsi_lpclk_ctrl;
        u32 dsi_phy_tmr_lpclk_cfg;
        u32 dsi_phy_tmr_cfg;
        u32 dsi_phy_rstz;
        u32 dsi_phy_if_cfg;
        u8 reserved4[0xac - 0xa4];
        u32 dsi_phy_status;
        u32 dsi_phy_tst_ctrl0;
        u32 dsi_phy_tst_ctrl1;
        u32 dsi_int_st0;
        u32 dsi_int_st1;
        u32 dsi_int_msk0;
        u32 dsi_int_msk1;
};
check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
 
#define RESET                           0
#define POWERUP                         BIT(0)
 
#define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
#define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
 
#define EN18_LOOSELY                    BIT(8)
#define DPI_COLOR_CODING_16BIT_1        0x0
#define DPI_COLOR_CODING_16BIT_2        0x1
#define DPI_COLOR_CODING_16BIT_3        0x2
#define DPI_COLOR_CODING_18BIT_1        0x3
#define DPI_COLOR_CODING_18BIT_2        0x4
#define DPI_COLOR_CODING_24BIT          0x5
 
#define COLORM_ACTIVE_LOW               BIT(4)
#define SHUTD_ACTIVE_LOW                BIT(3)
#define HSYNC_ACTIVE_LOW                BIT(2)
#define VSYNC_ACTIVE_LOW                BIT(1)
#define DATAEN_ACTIVE_LOW               BIT(0)
 
#define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
#define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
 
#define EN_CRC_RX                       BIT(4)
#define EN_ECC_RX                       BIT(3)
#define EN_BTA                          BIT(2)
#define EN_EOTP_RX                      BIT(1)
#define EN_EOTP_TX                      BIT(0)
 
#define ENABLE_VIDEO_MODE               0
#define ENABLE_CMD_MODE                 BIT(0)
 
#define FRAME_BTA_ACK                   BIT(14)
#define ENABLE_LOW_POWER                (0x3f << 8)
#define ENABLE_LOW_POWER_MASK           (0x3f << 8)
#define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0
#define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1
#define VID_MODE_TYPE_BURST             0x2
 
#define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
#define VID_PKT_MAX_SIZE                0x3fff
 
#define MAX_RD_PKT_SIZE_LP              BIT(24)
#define DCS_LW_TX_LP                    BIT(19)
#define DCS_SR_0P_TX_LP                 BIT(18)
#define DCS_SW_1P_TX_LP                 BIT(17)
#define DCS_SW_0P_TX_LP                 BIT(16)
#define GEN_LW_TX_LP                    BIT(14)
#define GEN_SR_2P_TX_LP                 BIT(13)
#define GEN_SR_1P_TX_LP                 BIT(12)
#define GEN_SR_0P_TX_LP                 BIT(11)
#define GEN_SW_2P_TX_LP                 BIT(10)
#define GEN_SW_1P_TX_LP                 BIT(9)
#define GEN_SW_0P_TX_LP                 BIT(8)
#define EN_ACK_RQST                     BIT(1)
#define EN_TEAR_FX                      BIT(0)
 
#define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
                                         DCS_LW_TX_LP | \
                                         DCS_SR_0P_TX_LP | \
                                         DCS_SW_1P_TX_LP | \
                                         DCS_SW_0P_TX_LP | \
                                         GEN_LW_TX_LP | \
                                         GEN_SR_2P_TX_LP | \
                                         GEN_SR_1P_TX_LP | \
                                         GEN_SR_0P_TX_LP | \
                                         GEN_SW_2P_TX_LP | \
                                         GEN_SW_1P_TX_LP | \
                                         GEN_SW_0P_TX_LP)
 
#define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
#define GEN_HDATA_MASK                  (0xffff << 8)
#define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
#define GEN_HTYPE_MASK                  0xff
 
#define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
#define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 
#define AUTO_CLKLANE_CTRL               BIT(1)
#define PHY_TXREQUESTCLKHS              BIT(0)
 
#define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
#define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 
#define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
#define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
#define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 
#define PHY_DISFORCEPLL                 0
#define PHY_ENFORCEPLL                  BIT(3)
#define PHY_DISABLECLK                  0
#define PHY_ENABLECLK                   BIT(2)
#define PHY_RSTZ                        0
#define PHY_UNRSTZ                      BIT(1)
#define PHY_SHUTDOWNZ                   0
#define PHY_UNSHUTDOWNZ                 BIT(0)
 
#define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
#define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 
#define LOCK                            BIT(0)
#define STOP_STATE_CLK_LANE             BIT(2)
 
#define PHY_TESTCLK                     BIT(1)
#define PHY_UNTESTCLK                   0
#define PHY_TESTCLR                     BIT(0)
#define PHY_UNTESTCLR                   0
 
#define PHY_TESTEN                      BIT(16)
#define PHY_UNTESTEN                    0
#define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
#define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 
#define BYPASS_VCO_RANGE        BIT(7)
#define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
#define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
#define VCO_IN_CAP_CON_LOW      (0x1 << 1)
#define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
#define REF_BIAS_CUR_SEL        BIT(0)
 
#define CP_CURRENT_1_5UA        0x0
#define CP_CURRENT_3UA          0x1
#define CP_CURRENT_4_5UA        0x2
#define CP_CURRENT_7_5UA        0x6
#define CP_CURRENT_6UA          0x9
#define CP_CURRENT_12UA         0xb
#define CP_CURRENT_SEL(val)     ((val) & 0xf)
 
#define CP_PROGRAM_EN           BIT(7)
 
#define LPF_PROGRAM_EN          BIT(6)
#define LPF_RESISTORS_15_5KOHM  0x1
#define LPF_RESISTORS_13KOHM    0x2
#define LPF_RESISTORS_11_5KOHM  0x4
#define LPF_RESISTORS_10_5KOHM  0x8
#define LPF_RESISTORS_8KOHM     0x10
#define LPF_RESISTORS_SEL(val)  ((val) & 0x3f)
 
#define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 
#define INPUT_DIVIDER(val)      ((val - 1) & 0x7f)
#define LOW_PROGRAM_EN          0
#define HIGH_PROGRAM_EN         BIT(7)
#define LOOP_DIV_LOW_SEL(val)   ((val - 1) & 0x1f)
#define LOOP_DIV_HIGH_SEL(val)  (((val - 1) >> 5) & 0xf)
#define PLL_LOOP_DIV_EN         BIT(5)
#define PLL_INPUT_DIV_EN        BIT(4)
 
#define POWER_CONTROL           BIT(6)
#define INTERNAL_REG_CURRENT    BIT(3)
#define BIAS_BLOCK_ON           BIT(2)
#define BANDGAP_ON              BIT(0)
 
#define TER_RESISTOR_HIGH       BIT(7)
#define TER_RESISTOR_LOW        0
#define LEVEL_SHIFTERS_ON       BIT(6)
#define TER_CAL_DONE            BIT(5)
#define SETRD_MAX               (0x7 << 2)
#define POWER_MANAGE            BIT(1)
#define TER_RESISTORS_ON        BIT(0)
 
#define BIASEXTR_SEL(val)       ((val) & 0x7)
#define BANDGAP_SEL(val)        ((val) & 0x7)
#define TLP_PROGRAM_EN          BIT(7)
#define THS_PRE_PROGRAM_EN      BIT(7)
#define THS_ZERO_PROGRAM_EN     BIT(6)
 
#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL                0x10
#define PLL_CP_CONTROL_PLL_LOCK_BYPASS                  0x11
#define PLL_LPF_AND_CP_CONTROL                          0x12
#define PLL_INPUT_DIVIDER_RATIO                         0x17
#define PLL_LOOP_DIVIDER_RATIO                          0x18
#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL       0x19
#define BANDGAP_AND_BIAS_CONTROL                        0x20
#define TERMINATION_RESISTER_CONTROL                    0x21
#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY         0x22
#define HS_RX_CONTROL_OF_LANE_0                         0x44
#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL     0x60
#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL     0x61
#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL     0x62
#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL       0x63
#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL        0x64
#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL              0x65
#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL      0x70
#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL      0x71
#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL      0x72
#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL        0x73
#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL         0x74
 
#define GEN_CMD_EMPTY                   BIT(0)
#define GEN_CMD_FULL                    BIT(1)
#define GEN_PLD_W_EMPTY                 BIT(2)
#define GEN_PLD_W_FULL                  BIT(3)
#define GEN_PLD_R_EMPTY                 BIT(4)
#define GEN_PLD_R_FULL                  BIT(5)
#define GEN_RD_CMD_BUSY                 BIT(6)
 
#define MIPI_INIT_CMD(...) { \
        .len = sizeof((char[]){__VA_ARGS__}), \
        .data = (char[]){__VA_ARGS__} }
 
enum mipi_dsi_pixel_format {
        MIPI_DSI_FMT_RGB888,
        MIPI_DSI_FMT_RGB666,
        MIPI_DSI_FMT_RGB666_PACKED,
        MIPI_DSI_FMT_RGB565,
};
 
enum {
        BANDGAP_97_07,
        BANDGAP_98_05,
        BANDGAP_99_02,
        BANDGAP_100_00,
        BANDGAP_93_17,
        BANDGAP_94_15,
        BANDGAP_95_12,
        BANDGAP_96_10,
};
 
enum {
        BIASEXTR_87_1,
        BIASEXTR_91_5,
        BIASEXTR_95_9,
        BIASEXTR_100,
        BIASEXTR_105_94,
        BIASEXTR_111_88,
        BIASEXTR_118_8,
        BIASEXTR_127_7,
};
 
enum rk_mipi_dsi_mode {
        MIPI_DSI_CMD_MODE,
        MIPI_DSI_VID_MODE,
};
 
struct dphy_pll_parameter_map {
        unsigned int max_mbps;
        u8 hsfreqrange;
        u8 icpctrl;
        u8 lpfctrl;
};
 
struct rk_mipi_dsi {
        struct rk_mipi_regs *mipi_regs;
        u64 lane_bps; /* per lane */
        u32 lanes;
        u32 format;
        u16 input_div;
        u16 feedback_div;
};
 
struct panel_init_command {
        int len;
        char *data;
};
 
struct mipi_panel_data {
        u8 mipi_num;
        enum mipi_dsi_pixel_format format;
        u8 lanes;
        u32 display_on_udelay;
        u32 video_mode_udelay;
        struct panel_init_command *init_cmd;
};
 
void rk_mipi_prepare(const struct edid *edid,
                     const struct mipi_panel_data *panel_data);
#endif